公开(公告)号：US20070042603A1

公开(公告)日：2007-02-22

申请号：US11367004

申请日：2006-03-02

申请人： Thomas Kropewnicki ,  Theodoros Panagopoulos ,  Nicolas Gani ,  Wilfred Pau ,  Meihua Shen ,  John Holland

发明人： Thomas Kropewnicki ,  Theodoros Panagopoulos ,  Nicolas Gani ,  Wilfred Pau ,  Meihua Shen ,  John Holland

IPC分类号： G01L21/30 ,  H01L21/302

CPC分类号： H01L21/32137 ,  H01L22/20

摘要： Embodiments of the invention generally provide methods for etching a substrate. In one embodiment, the method includes determining a substrate temperature target profile that corresponds to a uniform deposition rate of etch by-products on a substrate, preferentially regulating a temperature of a first portion of a substrate support relative to a second portion of the substrate support to obtain the substrate temperature target profile on the substrate, and etching the substrate on the preferentially regulated substrate support. In another embodiment, the method includes providing a substrate in a processing chamber having a selectable distribution of species within the processing chamber and a substrate support with lateral temperature control, wherein a temperature profile induced by the substrate support and a selection of species distribution comprise a control parameter set, etching a first layer of material and etching a second layer of material respectively using different control parameter sets.

摘要翻译： 本发明的实施例通常提供蚀刻衬底的方法。 在一个实施例中，该方法包括确定对应于衬底上的蚀刻副产物的均匀沉积速率的衬底温度目标分布，优选地调节衬底支撑件的第一部分相对于衬底支撑件的第二部分的温度 以获得衬底上的衬底温度目标曲线，并且在优先调节的衬底支撑件上蚀刻衬底。 在另一个实施例中，该方法包括在处理室中提供衬底，该处理室具有在处理室内的物质的可选择分布以及具有侧向温度控制的衬底支撑件，其中由衬底支撑件引导的温度曲线和物种分布的选择包括 控制参数集，蚀刻第一层材料并使用不同的控制参数集分别蚀刻第二层材料。

公开(公告)号：US07648914B2

公开(公告)日：2010-01-19

申请号：US11367004

申请日：2006-03-02

申请人： Thomas J. Kropewnicki ,  Theodoros Panagopoulos ,  Nicolas Gani ,  Wilfred Pau ,  Meihua Shen ,  John P. Holland

发明人： Thomas J. Kropewnicki ,  Theodoros Panagopoulos ,  Nicolas Gani ,  Wilfred Pau ,  Meihua Shen ,  John P. Holland

IPC分类号： H01L21/302

CPC分类号： H01L21/32137 ,  H01L22/20

摘要： Embodiments of the invention generally provide methods for etching a substrate. In one embodiment, the method includes determining a substrate temperature target profile that corresponds to a uniform deposition rate of etch by-products on a substrate, preferentially regulating a temperature of a first portion of a substrate support relative to a second portion of the substrate support to obtain the substrate temperature target profile on the substrate, and etching the substrate on the preferentially regulated substrate support. In another embodiment, the method includes providing a substrate in a processing chamber having a selectable distribution of species within the processing chamber and a substrate support with lateral temperature control, wherein a temperature profile induced by the substrate support and a selection of species distribution comprise a control parameter set, etching a first layer of material and etching a second layer of material respectively using different control parameter sets.

摘要翻译： 本发明的实施例通常提供蚀刻衬底的方法。 在一个实施例中，该方法包括确定对应于衬底上的蚀刻副产物的均匀沉积速率的衬底温度目标分布，优选地调节衬底支撑件的第一部分相对于衬底支撑件的第二部分的温度 以获得衬底上的衬底温度目标曲线，并且在优先调节的衬底支撑件上蚀刻衬底。 在另一个实施例中，该方法包括在处理室中提供衬底，该处理室具有在处理室内的物质的可选择分布以及具有侧向温度控制的衬底支撑件，其中由衬底支撑件引导的温度曲线和物种分布的选择包括 控制参数集，蚀刻第一层材料并使用不同的控制参数集分别蚀刻第二层材料。

公开(公告)号：US07436645B2

公开(公告)日：2008-10-14

申请号：US11531474

申请日：2006-09-13

申请人： John Holland ,  Theodoros Panagopoulos ,  Alexander Matyushkin ,  Dan Katz ,  Michael F. Hegarty ,  Denis M. Koosau ,  Nicolas Gani

发明人： John Holland ,  Theodoros Panagopoulos ,  Alexander Matyushkin ,  Dan Katz ,  Michael F. Hegarty ,  Denis M. Koosau ,  Nicolas Gani

IPC分类号： H01T23/00

CPC分类号： H01L21/67109 ,  H01L21/67103 ,  H01L21/6831

摘要： A pedestal assembly and method for controlling temperature of a substrate during processing is provided. In one embodiment, the pedestal assembly includes an electrostatic chuck coupled to a metallic base. The electrostatic chuck includes at least one chucking electrode and metallic base includes at least two fluidly isolated conduit loops disposed therein. In another embodiment, the pedestal assembly includes a support member that is coupled to a base by a material layer. The material layer has at least two regions having different coefficients of thermal conductivity. In another embodiment, the support member is an electrostatic chuck. In further embodiments, a pedestal assembly has channels formed between the base and support member for providing cooling gas in proximity to the material layer to further control heat transfer between the support member and the base, thereby controlling the temperature profile of a substrate disposed on the support member.

摘要翻译： 提供了一种用于在处理期间控制基板的温度的基座组件和方法。 在一个实施例中，基座组件包括联接到金属基座的静电卡盘。 静电吸盘包括至少一个夹紧电极和金属底座，其包括设置在其中的至少两个流体隔离的导管环。 在另一个实施例中，基座组件包括通过材料层联接到基座的支撑构件。 材料层具有至少两个具有不同导热系数的区域。 在另一个实施例中，支撑构件是静电卡盘。 在另外的实施例中，基座组件具有形成在基部和支撑构件之间的通道，用于在材料层附近提供冷却气体，以进一步控制支撑构件和基座之间的热传递，由此控制设置在基座上的基板的温度分布 支持会员

公开(公告)号：US20070139856A1

公开(公告)日：2007-06-21

申请号：US11531474

申请日：2006-09-13

申请人： John Holland ,  Theodoros Panagopoulos ,  Alexander Matyushkin ,  Dan Katz ,  Michael Hegarty ,  Denis Koosau ,  Nicolas Gani

发明人： John Holland ,  Theodoros Panagopoulos ,  Alexander Matyushkin ,  Dan Katz ,  Michael Hegarty ,  Denis Koosau ,  Nicolas Gani

IPC分类号： H01T23/00

CPC分类号： H01L21/67109 ,  H01L21/67103 ,  H01L21/6831

摘要： A pedestal assembly and method for controlling temperature of a substrate during processing is provided. In one embodiment, the pedestal assembly includes an electrostatic chuck coupled to a metallic base. The electrostatic chuck includes at least one chucking electrode and metallic base includes at least two fluidly isolated conduit loops disposed therein. In another embodiment, the pedestal assembly includes a support member that is coupled to a base by a material layer. The material layer has at least two regions having different coefficients of thermal conductivity. In another embodiment, the support member is an electrostatic chuck. In further embodiments, a pedestal assembly has channels formed between the base and support member for providing cooling gas in proximity to the material layer to further control heat transfer between the support member and the base, thereby controlling the temperature profile of a substrate disposed on the support member.

摘要翻译： 提供了一种用于在处理期间控制基板的温度的基座组件和方法。 在一个实施例中，基座组件包括联接到金属基座的静电卡盘。 静电吸盘包括至少一个夹紧电极和金属底座，其包括设置在其中的至少两个流体隔离的导管环。 在另一个实施例中，基座组件包括通过材料层联接到基座的支撑构件。 材料层具有至少两个具有不同导热系数的区域。 在另一个实施例中，支撑构件是静电卡盘。 在另外的实施例中，基座组件具有形成在基部和支撑构件之间的通道，用于在材料层附近提供冷却气体，以进一步控制支撑构件和基座之间的热传递，由此控制设置在基座上的基板的温度分布 支持会员

公开(公告)号：US20130087174A1

公开(公告)日：2013-04-11

申请号：US13614365

申请日：2012-09-13

申请人： Noel Sun ,  Meihua Shen ,  Nicolas Gani ,  Chung Nang Liu ,  Radhika C. Mani

发明人： Noel Sun ,  Meihua Shen ,  Nicolas Gani ,  Chung Nang Liu ,  Radhika C. Mani

IPC分类号： B08B5/00

CPC分类号： B08B5/00 ,  B08B7/0035 ,  C23C16/4405 ,  H01J37/32449 ,  H01J37/32862 ,  Y10S438/905

摘要： Embodiments of the invention include methods for in-situ chamber dry cleaning a plasma processing chamber utilized for gate structure fabrication process in semiconductor devices. In one embodiment, a method for in-situ chamber dry clean includes supplying a first cleaning gas including at least a boron containing gas into a processing chamber in absence of a substrate disposed therein, supplying a second cleaning gas including at least a halogen containing gas into the processing chamber in absence of the substrate, and supplying a third cleaning gas including at least an oxygen containing gas into the processing chamber in absence of the substrate.

摘要翻译： 本发明的实施例包括用于半导体器件中用于栅极结构制造工艺的等离子体处理室的原位室干洗的方法。 在一个实施例中，一种用于原位室干洗的方法包括在不存在设置在其中的基板的情况下将包括至少含硼气体的第一清洁气体供应到处理室中，提供至少包含含卤素气体的第二清洁气体 在没有基板的情况下进入处理室，并且在没有基板的情况下将至少包含含氧气体的第三清洁气体供应到处理室中。

公开(公告)号：US20090221149A1

公开(公告)日：2009-09-03

申请号：US12039262

申请日：2008-02-28

申请人： Edward P. Hammond, IV ,  Rodolfo P. Belen ,  Nicolas Gani ,  Jing Zou ,  Meihua Shen ,  Michael D. Willwerth ,  David Palagashvili

发明人： Edward P. Hammond, IV ,  Rodolfo P. Belen ,  Nicolas Gani ,  Jing Zou ,  Meihua Shen ,  Michael D. Willwerth ,  David Palagashvili

IPC分类号： H01L21/306

CPC分类号： H01J37/32449 ,  H01J37/3244

摘要： An apparatus having a multiple gas injection port system for providing a high uniform etching rate across the substrate is provided. In one embodiment, the apparatus includes a nozzle in the semiconductor processing apparatus having a hollow cylindrical body having a first outer diameter defining a hollow cylindrical sleeve and a second outer diameter defining a tip, a longitudinal passage formed longitudinally through the body of the hollow cylindrical sleeve and at least partially extending to the tip, and a lateral passage formed in the tip coupled to the longitudinal passage, the lateral passage extending outward from the longitudinal passage having an opening formed on an outer surface of the tip.

摘要翻译： 提供了一种具有多个气体注入端口系统的设备，用于在衬底上提供高均匀的蚀刻速率。 在一个实施例中，该设备包括在半导体处理设备中的喷嘴，其具有中空圆柱体，其具有限定中空圆柱形套筒的第一外径和限定尖端的第二外径，纵向通道纵向穿过中空圆柱体 并且至少部分地延伸到尖端，以及形成在连接到纵向通道的尖端中的侧向通道，从纵向通道向外延伸的侧向通道具有形成在尖端的外表面上的开口。

公开(公告)号：US06599437B2

公开(公告)日：2003-07-29

申请号：US09813392

申请日：2001-03-20

申请人： Oranna Yauw ,  Meihua Shen ,  Nicolas Gani ,  Jeffrey D. Chinn

发明人： Oranna Yauw ,  Meihua Shen ,  Nicolas Gani ,  Jeffrey D. Chinn

IPC分类号： H01L213213

CPC分类号： H01L21/0276 ,  H01L21/31138

摘要： A two-step method of etching an organic coating layer, in particular, an organic antireflection coating (ARC) layer, is disclosed. During the main etch step, the organic coating layer is etched using a plasma generated from a first source gas which includes a fluorocarbon and a non-carbon-containing, halogen-comprising gas. Etching is performed using a first substrate bias power. During the overetch step, residual organic coating material remaining after the main etch step is removed by exposing the substrate to a plasma generated from a second source gas which includes a chlorine-containing gas and an oxygen-containing gas, and which does not include a polymer-forming gas. The overetch step is performed using a second substrate bias power which is less than the first substrate bias power. The first source gas and first substrate bias power provide a higher etch rate in dense feature areas than in isolated feature areas during the main etch step, whereas the second source gas and second substrate bias power provide a higher etch rate in isolated feature areas than in dense feature areas during the overetch step, resulting in an overall balancing effect.

摘要翻译： 公开了蚀刻有机涂层，特别是有机抗反射涂层（ARC）层的两步法。 在主蚀刻步骤期间，使用由包括碳氟化合物和非含碳卤素气体的第一源气体产生的等离子体蚀刻有机涂层。 使用第一衬底偏置功率进行蚀刻。 在过蚀刻步骤期间，通过将衬底暴露于由包含含氯气体和含氧气体的第二源气体产生的等离子体而将主蚀刻步骤后剩余的残留有机涂层材料除去，并且不包括 聚合物形成气体。 使用小于第一衬底偏置功率的第二衬底偏置功率来执行过蚀刻步骤。 在主蚀刻步骤期间，第一源气体和第一衬底偏置功率在致密特征区域中提供比在隔离特征区域中更高的蚀刻速率，而第二源气体和第二衬底偏置功率在隔离特征区域中提供比在 在疏浚过程中密集的特征区域，导致整体平衡效果。

公开(公告)号：US09533332B2

公开(公告)日：2017-01-03

申请号：US13614365

申请日：2012-09-13

申请人： Noel Sun ,  Meihua Shen ,  Nicolas Gani ,  Chung Nang Liu ,  Radhika C. Mani

发明人： Noel Sun ,  Meihua Shen ,  Nicolas Gani ,  Chung Nang Liu ,  Radhika C. Mani

IPC分类号： B08B5/00 ,  B08B7/00 ,  B08B9/08 ,  C23C16/44 ,  H01J37/32

CPC分类号： B08B5/00 ,  B08B7/0035 ,  C23C16/4405 ,  H01J37/32449 ,  H01J37/32862 ,  Y10S438/905

摘要： Embodiments of the invention include methods for in-situ chamber dry cleaning a plasma processing chamber utilized for gate structure fabrication process in semiconductor devices. In one embodiment, a method for in-situ chamber dry clean includes supplying a first cleaning gas including at least a boron containing gas into a processing chamber in absence of a substrate disposed therein, supplying a second cleaning gas including at least a halogen containing gas into the processing chamber in absence of the substrate, and supplying a third cleaning gas including at least an oxygen containing gas into the processing chamber in absence of the substrate.

摘要翻译： 本发明的实施例包括用于半导体器件中用于栅极结构制造工艺的等离子体处理室的原位室干洗的方法。 在一个实施例中，一种用于原位室干洗的方法包括在不存在设置在其中的基板的情况下将包括至少含硼气体的第一清洁气体供应到处理室中，提供至少包含含卤素气体的第二清洁气体 在没有基板的情况下进入处理室，并且在没有基板的情况下将至少包含含氧气体的第三清洁气体供应到处理室中。

公开(公告)号：US20100210112A1

公开(公告)日：2010-08-19

申请号：US12371085

申请日：2009-02-13

申请人： Meihua Shen ,  Noel Sun ,  Nicolas Gani ,  Han-Hsiang Chen ,  Eric Pei ,  Weimin Zeng ,  Thorsten B. Lill ,  Uday Mitra ,  Ellie Y. Yieh

发明人： Meihua Shen ,  Noel Sun ,  Nicolas Gani ,  Han-Hsiang Chen ,  Eric Pei ,  Weimin Zeng ,  Thorsten B. Lill ,  Uday Mitra ,  Ellie Y. Yieh

IPC分类号： H01L21/3065

CPC分类号： H01L21/31122 ,  H01L21/28123 ,  H01L21/28167 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/32139 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： Methods for fabricating a semiconductor device having a lanthanum-family-based oxide layer are described. A gate stack having a lanthanum-family-based oxide layer is provided above a substrate. At least a portion of the lanthanum-family-based oxide layer is modified to form a lanthanum-family-based halide portion. The lanthanum-family-based halide portion is removed with a water vapor treatment.

摘要翻译： 描述了制造具有镧族氧化物层的半导体器件的方法。 具有镧族氧化物层的栅极叠层设置在基板的上方。 镧族氧化物层的至少一部分被改性以形成镧族卤化物部分。 用水蒸气处理除去镧族卤化物部分。

公开(公告)号：US20070249182A1

公开(公告)日：2007-10-25

申请号：US11736562

申请日：2007-04-17

申请人： Radhika Mani ,  Nicolas Gani ,  Wei Liu ,  Meihua Shen ,  Shashank C. Deshmukh

发明人： Radhika Mani ,  Nicolas Gani ,  Wei Liu ,  Meihua Shen ,  Shashank C. Deshmukh

IPC分类号： H01L21/302 ,  H01L21/31

CPC分类号： H01L21/31116 ,  H01L21/31122 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 100° C. and 350° C., and etching the wafer with a selectivity of high K dielectric to oxide or nitride greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a reactive ion etch processing chamber by applying a bias power to the wafer, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a an inductively coupled plasma processing chamber by applying a bias power to the wafer, applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1.

摘要翻译： 具有高K电介质层和含氧化物或氮化物的层的晶片在电感耦合等离子体处理室中被蚀刻，通过施加源功率以产生电感耦合等离子体，将包含BCl 3 >，将晶片的温度设置在100℃和350℃之间，并且以大于10:1的氧化物或氮化物的高K电介质的选择性蚀刻晶片。 具有氧化物层和氮化物层的晶片通过向晶片施加偏置功率而在反应离子蚀刻处理室中进行蚀刻，将包含BCl 3 3的气体引入室中，设定晶片的温度 在20℃和200℃之间，并且以大于10:1的氧化物至氮化物选择性蚀刻晶片。 在电感耦合等离子体处理室中蚀刻具有氧化物层和氮化物层的晶片，通过向晶片施加偏置功率，施加源电力以产生电感耦合等离子体，将包括BCI 3，将晶片的温度设定在20℃至200℃之间，并以大于10:1的氧化物至氮化物选择性蚀刻晶片。