-
公开(公告)号：US07480830B2
公开(公告)日：2009-01-20
申请号：US11937568
申请日：2007-11-09
IPC分类号： G06F11/00
CPC分类号： G11C29/16 , G11C5/04 , G11C29/022 , G11C2029/4002
摘要： A buffered memory module including a downstream buffer, a downstream receiver, an upstream driver, an upstream receiver. The downstream buffer and the downstream receiver are both adapted for connection to a downstream memory bus in a packetized cascaded interconnect memory subsystem. The upstream driver and the upstream receiver are both adapted for connection to an upstream memory bus in the memory subsystem. During a test of the memory module, the upstream driver is connected to the downstream receiver and the downstream driver is connected to the upstream receiver. The memory module also includes one or more storage registers, a microprocessor and a service interface port. The microprocessor includes instructions for executing the test of the memory module including storing results of the test in the storage registers. The service interface port receives service interface signals that initiate the execution of the test and accesses the storage registers to determine the results of the test.
摘要翻译： 缓冲存储器模块，包括下游缓冲器，下游接收器，上游驱动器，上游接收器。 下游缓冲器和下游接收器都适于连接到分组级联互连存储器子系统中的下游存储器总线。 上游驱动器和上游接收器都适于连接到存储器子系统中的上游存储器总线。 在对存储器模块进行测试期间，上游驱动器连接到下游接收器，下游驱动器连接到上游接收器。 存储器模块还包括一个或多个存储寄存器，微处理器和服务接口端口。 微处理器包括用于执行存储器模块的测试的指令，包括将测试结果存储在存储寄存器中。 服务接口端口接收启动测试执行的服务接口信号，并访问存储寄存器以确定测试结果。
-
公开(公告)号：US07356737B2
公开(公告)日：2008-04-08
申请号：US10977922
申请日：2004-10-29
IPC分类号： G06F11/00
CPC分类号： G11C29/16 , G11C5/04 , G11C29/022 , G11C2029/4002
摘要： A buffered memory module including a downstream buffer, a downstream receiver, an upstream driver, an upstream receiver. The downstream buffer and the downstream receiver are both adapted for connection to a downstream memory bus in a packetized cascaded interconnect memory subsystem. The upstream driver and the upstream receiver are both adapted for connection to an upstream memory bus in the memory subsystem. During a test of the memory module, the upstream driver is connected to the downstream receiver and the downstream driver is connected to the upstream receiver. The memory module also includes one or more storage registers, a microprocessor and a service interface port. The microprocessor includes instructions for executing the test of the memory module including storing results of the test in the storage registers. The service interface port receives service interface signals that initiate the execution of the test and accesses the storage registers to determine the results of the test.
摘要翻译： 缓冲存储器模块，包括下游缓冲器，下游接收器，上游驱动器，上游接收器。 下游缓冲器和下游接收器都适于连接到分组级联互连存储器子系统中的下游存储器总线。 上游驱动器和上游接收器都适于连接到存储器子系统中的上游存储器总线。 在对存储器模块进行测试期间，上游驱动器连接到下游接收器，下游驱动器连接到上游接收器。 存储器模块还包括一个或多个存储寄存器，微处理器和服务接口端口。 微处理器包括用于执行存储器模块的测试的指令，包括将测试结果存储在存储寄存器中。 服务接口端口接收启动测试执行的服务接口信号，并访问存储寄存器以确定测试结果。
-
3.发明授权System, method and storage medium for providing a high speed test interface to a memory subsystem 有权用于向存储器子系统提供高速测试接口的系统，方法和存储介质公开(公告)号：US07475316B2
公开(公告)日：2009-01-06
申请号：US11971578
申请日：2008-01-09
申请人： Thomas M. Cowell , Kevin C. Gower , Frank LaPietra
发明人： Thomas M. Cowell , Kevin C. Gower , Frank LaPietra
CPC分类号： G11C29/48 , G11C5/00 , G11C5/04 , G11C29/1201
摘要： A buffer device for testing a memory subsystem. The buffer device includes a parallel bus port adapted for connection to a slow speed bus and a serial bus port adapted for connection to a high speed bus. The high speed bus operates at a faster speed than the slow speed bus. The buffer device also includes a bus converter having a standard operating mode for converting serial packetized input data received via the serial bus port into parallel bus output data for output via the parallel bus port. The buffer device also includes an alternate operating mode for converting parallel bus input data received via the parallel bus port into serial packetized output data for output via the serial bus port. The serial packetized input data is consistent in function and timing to the serial packetized output data.
摘要翻译： 用于测试存储器子系统的缓冲器。 缓冲装置包括适于连接到低速总线的并行总线端口和适于连接到高速总线的串行总线端口。 高速总线以比慢速总线更快的速度运行。 缓冲装置还包括总线转换器，其具有用于将经由串行总线端口接收的串行分组化输入数据转换为并行总线输出数据的标准操作模式，以经由并行总线端口输出。 缓冲装置还包括用于将经由并行总线端口接收的并行总线输入数据转换为串行分组化输出数据以供经由串行总线端口输出的备用操作模式。 串行打包输入数据在串行打包输出数据的功能和时序上是一致的。
-
4.发明授权System, method and storage medium for providing a high speed test interface to a memory subsystem 有权用于向存储器子系统提供高速测试接口的系统，方法和存储介质公开(公告)号：US07395476B2
公开(公告)日：2008-07-01
申请号：US10977790
申请日：2004-10-29
申请人： Thomas M. Cowell , Kevin C. Gower , Frank LaPietra
发明人： Thomas M. Cowell , Kevin C. Gower , Frank LaPietra
CPC分类号： G11C29/48 , G11C5/00 , G11C5/04 , G11C29/1201
摘要： A buffer device for testing a memory subsystem. The buffer device includes a parallel bus port adapted for connection to a slow speed bus and a serial bus port adapted for connection to a high speed bus. The high speed bus operates at a faster speed than the slow speed bus. The buffer device also includes a bus converter having a standard operating mode for converting serial packetized input data received via the serial bus port into parallel bus output data for output via the parallel bus port. The buffer device also includes an alternate operating mode for converting parallel bus input data received via the parallel bus port into serial packetized output data for output via the serial bus port. The serial packetized input data is consistent in function and timing to the serial packetized output data.
摘要翻译： 用于测试存储器子系统的缓冲设备。 缓冲装置包括适于连接到低速总线的并行总线端口和适于连接到高速总线的串行总线端口。 高速总线以比慢速总线更快的速度运行。 缓冲装置还包括总线转换器，其具有用于将经由串行总线端口接收的串行分组化输入数据转换为并行总线输出数据的标准操作模式，以经由并行总线端口输出。 缓冲装置还包括用于将经由并行总线端口接收的并行总线输入数据转换为串行分组化输出数据以供经由串行总线端口输出的备用操作模式。 串行打包输入数据在串行打包输出数据的功能和时序上是一致的。
-
公开(公告)号：US07895374B2
公开(公告)日：2011-02-22
申请号：US12165809
申请日：2008-07-01
CPC分类号： G06F13/4243 , G06F11/2007 , G06F11/2017 , Y02D10/14 , Y02D10/151
摘要： A communication interface device, system, method, and design structure for providing dynamic segment sparing and repair in a memory system. The communication interface device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.
摘要翻译： 用于在存储器系统中提供动态段保存和修复的通信接口设备，系统，方法和设计结构。 通信接口装置包括驱动侧切换逻辑，包括驱动器多路复用器，用于选择用于在总线的链路段上发送的驱动器数据，以及包括接收机多路复用器的接收侧切换逻辑，以从总线的链路段选择接收的数据。 该总线包括多个数据链路段，一个时钟链路段，以及由驱动器侧切换逻辑和接收侧切换逻辑选择的至少两个备用链路段，用于替换一个或多个数据链路段和时钟链路段 。
-
公开(公告)号：US20100005345A1
公开(公告)日：2010-01-07
申请号：US12165799
申请日：2008-07-01
IPC分类号： G06F11/00
CPC分类号： G06F11/167 , G06F11/073 , G06F11/076 , G06F11/1004 , G06F11/2007 , G11C5/04 , G11C29/02 , G11C29/022
摘要： A communication interface device, system, method, and design structure for bit shadowing in a memory system are provided. The communication interface device includes shadow selection logic to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. The communication interface device also includes shadow compare logic to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
摘要翻译： 提供了一种用于存储器系统中的位阴影的通信接口设备，系统，方法和设计结构。 通信接口设备包括用于选择驱动器位位置作为阴影驱动器值的阴影选择逻辑，以及线驱动器，以在总线的单独链路段上传送所选择的驱动器位位置和阴影驱动器值的数据。 通信接口设备还包括阴影比较逻辑，以将所选择的接收值与来自总线的阴影接收值进行比较，并且识别响应于比较不匹配的错误比较，以及阴影计数器来计数相对于总线的误比率 错误率在一段时间内。 响应于在总线错误率的预定阈值内的错误比较的速率来识别有缺陷的链路段。
-
公开(公告)号：US20090094476A1
公开(公告)日：2009-04-09
申请号：US12332396
申请日：2008-12-11
CPC分类号： G06F13/4234 , G06F13/1689
摘要： A computer program product and a hub device for deriving clocks in a memory system are provided. The computer program product includes a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for facilitating a method. The method includes receiving a reference oscillator clock at the hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.
摘要翻译： 提供了一种用于在存储器系统中导出时钟的计算机程序产品和集线器设备。 计算机程序产品包括可由处理电路读取的存储介质，并且存储由处理电路执行以便于方法的指令。 该方法包括在集线器设备处接收参考振荡器时钟。 集线器设备经由控制器接口与控制器通道通信，并且经由存储器接口与存储器设备通信。 以基准时钟频率工作的基本时钟从参考振荡器时钟导出。 通过将基本时钟乘以存储器乘法器导出存储器接口时钟。 控制器接口时钟是通过将基本时钟与控制器乘法器相乘得出的。 存储器接口时钟应用于存储器接口，控制器接口时钟应用于控制器接口。
-
公开(公告)号：US20110075740A1
公开(公告)日：2011-03-31
申请号：US12568765
申请日：2009-09-29
IPC分类号： H04B3/00
CPC分类号： H04L25/0272 , Y02D30/30
摘要： An electronic system having a power efficient differential signal between a first and second electronic unit. A controller uses information, such as compliance with data transmission rate requirement and bit error rate (BER) versus a BER threshold to control power modes such that a minimal amount of power is required. Amplitude of transmission and single ended or differential transmission of data are examples of the power modes. The controller also factors in a failing phase in a differential signal in selecting a minimal power mode that satisfies the transmission rate requirement of the BER threshold.
摘要翻译： 一种在第一和第二电子单元之间具有功率有效的差分信号的电子系统。 控制器使用诸如符合数据传输速率要求和误码率（BER）与BER阈值的信息来控制功率模式，使得需要最小量的功率。 传输幅度和数据的单端或差分传输是功率模式的例子。 控制器还在选择满足BER阈值的传输速率要求的最小功率模式时，在差分信号中导致故障相位。
-
公开(公告)号：US20100005349A1
公开(公告)日：2010-01-07
申请号：US12165848
申请日：2008-07-01
IPC分类号： G06F11/00
CPC分类号： G06F11/2007 , G06F11/0724 , G06F11/076 , H04L1/20
摘要： A processing device, processing system, method, and design structure for an enhanced microprocessor interconnect with bit shadowing are provided. The processing device includes shadow selection logic to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. The processing device also includes shadow compare logic to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
摘要翻译： 提供了一种用于具有位阴影的增强型微处理器互连的处理装置，处理系统，方法和设计结构。 处理装置包括阴影选择逻辑以选择驱动器位位置作为阴影驱动器值，以及线驱动器，用于在总线的单独链路段上传送所选择的驱动器位位置和阴影驱动器值的数据。 处理装置还包括阴影比较逻辑，以将所选接收值与来自总线的阴影接收值进行比较，并根据比较不匹配识别错误比较，并且阴影计数器计数误差相对于总线误差的速率 率一段时间。 响应于在总线错误率的预定阈值内的错误比较的速率来识别有缺陷的链路段。
-
10.发明授权System, method and storage medium for bus calibration in a memory subsystem 失效用于内存子系统总线校准的系统，方法和存储介质公开(公告)号：US07590882B2
公开(公告)日：2009-09-15
申请号：US11780556
申请日：2007-07-20
申请人： Frank D. Ferraiolo , Kevin C. Gower
发明人： Frank D. Ferraiolo , Kevin C. Gower
CPC分类号： G06F13/4239
摘要： A cascaded interconnect system with one or more memory modules, a memory controller and a memory bus that utilizes periodic recalibration. The memory modules and the memory controller are directly interconnected by a packetized multi-transfer interface via the memory bus and provide scrambled data for use in the periodic recalibration.
摘要翻译： 具有一个或多个存储器模块的级联互连系统，存储器控制器和利用定期重新校准的存储器总线。 存储器模块和存储器控制器通过存储器总线通过分组化的多传输接口直接互连，并提供用于定期重新校准的加扰数据。
-
-
-
-
-
-
-
-
-
搜索结果
203 条记录 (耗时 0.026 秒)
