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公开(公告)号：US07356737B2
公开(公告)日：2008-04-08
申请号：US10977922
申请日：2004-10-29
IPC分类号： G06F11/00
CPC分类号： G11C29/16 , G11C5/04 , G11C29/022 , G11C2029/4002
摘要： A buffered memory module including a downstream buffer, a downstream receiver, an upstream driver, an upstream receiver. The downstream buffer and the downstream receiver are both adapted for connection to a downstream memory bus in a packetized cascaded interconnect memory subsystem. The upstream driver and the upstream receiver are both adapted for connection to an upstream memory bus in the memory subsystem. During a test of the memory module, the upstream driver is connected to the downstream receiver and the downstream driver is connected to the upstream receiver. The memory module also includes one or more storage registers, a microprocessor and a service interface port. The microprocessor includes instructions for executing the test of the memory module including storing results of the test in the storage registers. The service interface port receives service interface signals that initiate the execution of the test and accesses the storage registers to determine the results of the test.
摘要翻译： 缓冲存储器模块，包括下游缓冲器，下游接收器，上游驱动器，上游接收器。 下游缓冲器和下游接收器都适于连接到分组级联互连存储器子系统中的下游存储器总线。 上游驱动器和上游接收器都适于连接到存储器子系统中的上游存储器总线。 在对存储器模块进行测试期间，上游驱动器连接到下游接收器，下游驱动器连接到上游接收器。 存储器模块还包括一个或多个存储寄存器，微处理器和服务接口端口。 微处理器包括用于执行存储器模块的测试的指令，包括将测试结果存储在存储寄存器中。 服务接口端口接收启动测试执行的服务接口信号，并访问存储寄存器以确定测试结果。
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2.发明授权System, method and storage medium for providing a high speed test interface to a memory subsystem 有权用于向存储器子系统提供高速测试接口的系统，方法和存储介质公开(公告)号：US07475316B2
公开(公告)日：2009-01-06
申请号：US11971578
申请日：2008-01-09
申请人： Thomas M. Cowell , Kevin C. Gower , Frank LaPietra
发明人： Thomas M. Cowell , Kevin C. Gower , Frank LaPietra
CPC分类号： G11C29/48 , G11C5/00 , G11C5/04 , G11C29/1201
摘要： A buffer device for testing a memory subsystem. The buffer device includes a parallel bus port adapted for connection to a slow speed bus and a serial bus port adapted for connection to a high speed bus. The high speed bus operates at a faster speed than the slow speed bus. The buffer device also includes a bus converter having a standard operating mode for converting serial packetized input data received via the serial bus port into parallel bus output data for output via the parallel bus port. The buffer device also includes an alternate operating mode for converting parallel bus input data received via the parallel bus port into serial packetized output data for output via the serial bus port. The serial packetized input data is consistent in function and timing to the serial packetized output data.
摘要翻译： 用于测试存储器子系统的缓冲器。 缓冲装置包括适于连接到低速总线的并行总线端口和适于连接到高速总线的串行总线端口。 高速总线以比慢速总线更快的速度运行。 缓冲装置还包括总线转换器，其具有用于将经由串行总线端口接收的串行分组化输入数据转换为并行总线输出数据的标准操作模式，以经由并行总线端口输出。 缓冲装置还包括用于将经由并行总线端口接收的并行总线输入数据转换为串行分组化输出数据以供经由串行总线端口输出的备用操作模式。 串行打包输入数据在串行打包输出数据的功能和时序上是一致的。
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公开(公告)号：US07480830B2
公开(公告)日：2009-01-20
申请号：US11937568
申请日：2007-11-09
IPC分类号： G06F11/00
CPC分类号： G11C29/16 , G11C5/04 , G11C29/022 , G11C2029/4002
摘要： A buffered memory module including a downstream buffer, a downstream receiver, an upstream driver, an upstream receiver. The downstream buffer and the downstream receiver are both adapted for connection to a downstream memory bus in a packetized cascaded interconnect memory subsystem. The upstream driver and the upstream receiver are both adapted for connection to an upstream memory bus in the memory subsystem. During a test of the memory module, the upstream driver is connected to the downstream receiver and the downstream driver is connected to the upstream receiver. The memory module also includes one or more storage registers, a microprocessor and a service interface port. The microprocessor includes instructions for executing the test of the memory module including storing results of the test in the storage registers. The service interface port receives service interface signals that initiate the execution of the test and accesses the storage registers to determine the results of the test.
摘要翻译： 缓冲存储器模块，包括下游缓冲器，下游接收器，上游驱动器，上游接收器。 下游缓冲器和下游接收器都适于连接到分组级联互连存储器子系统中的下游存储器总线。 上游驱动器和上游接收器都适于连接到存储器子系统中的上游存储器总线。 在对存储器模块进行测试期间，上游驱动器连接到下游接收器，下游驱动器连接到上游接收器。 存储器模块还包括一个或多个存储寄存器，微处理器和服务接口端口。 微处理器包括用于执行存储器模块的测试的指令，包括将测试结果存储在存储寄存器中。 服务接口端口接收启动测试执行的服务接口信号，并访问存储寄存器以确定测试结果。
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4.发明授权System, method and storage medium for providing a high speed test interface to a memory subsystem 有权用于向存储器子系统提供高速测试接口的系统，方法和存储介质公开(公告)号：US07395476B2
公开(公告)日：2008-07-01
申请号：US10977790
申请日：2004-10-29
申请人： Thomas M. Cowell , Kevin C. Gower , Frank LaPietra
发明人： Thomas M. Cowell , Kevin C. Gower , Frank LaPietra
CPC分类号： G11C29/48 , G11C5/00 , G11C5/04 , G11C29/1201
摘要： A buffer device for testing a memory subsystem. The buffer device includes a parallel bus port adapted for connection to a slow speed bus and a serial bus port adapted for connection to a high speed bus. The high speed bus operates at a faster speed than the slow speed bus. The buffer device also includes a bus converter having a standard operating mode for converting serial packetized input data received via the serial bus port into parallel bus output data for output via the parallel bus port. The buffer device also includes an alternate operating mode for converting parallel bus input data received via the parallel bus port into serial packetized output data for output via the serial bus port. The serial packetized input data is consistent in function and timing to the serial packetized output data.
摘要翻译： 用于测试存储器子系统的缓冲设备。 缓冲装置包括适于连接到低速总线的并行总线端口和适于连接到高速总线的串行总线端口。 高速总线以比慢速总线更快的速度运行。 缓冲装置还包括总线转换器，其具有用于将经由串行总线端口接收的串行分组化输入数据转换为并行总线输出数据的标准操作模式，以经由并行总线端口输出。 缓冲装置还包括用于将经由并行总线端口接收的并行总线输入数据转换为串行分组化输出数据以供经由串行总线端口输出的备用操作模式。 串行打包输入数据在串行打包输出数据的功能和时序上是一致的。
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公开(公告)号：US07224595B2
公开(公告)日：2007-05-29
申请号：US10903371
申请日：2004-07-30
CPC分类号： G11C5/04
摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.
摘要翻译： 双列直插式存储器模块（DIMM）包括具有大约151.2至大约151.5毫米的长度的卡，连接到卡的多个单独的本地存储器件以及连接到卡的缓冲器装置，缓冲器装置被配置为将 打包内存界面。 该卡片包括至少276个配置在其上的针脚。
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6.发明申请ERROR CORRECTING CODE PROTECTED QUASI-STATIC BIT COMMUNICATION ON A HIGH-SPEED BUS 失效高速总线上的错误纠正代码保护的静态位通信公开(公告)号：US20120272119A1
公开(公告)日：2012-10-25
申请号：US13535574
申请日：2012-06-28
摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.
摘要翻译： 提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。 通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。 通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。
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公开(公告)号：US08245105B2
公开(公告)日：2012-08-14
申请号：US12166235
申请日：2008-07-01
IPC分类号： H03M13/00
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/0781 , G06F11/1004 , G11C5/04 , G11C29/70 , G11C2029/0409 , G11C2029/0411
摘要： A hub device, memory system, and method for providing a cascade interconnect memory system with enhanced reliability. The hub device includes an interface to a high-speed bus for communicating with a memory controller. The memory controller and the hub device are included in a cascade interconnect memory system and the high-speed bus includes bit lanes and one or more clock lanes. The hub device also includes a bi-directional fault signal line in communication with the memory controller and readable by a service interface. The hub device also includes a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures. In addition, the hub device includes error recovery logic for responding to a failure detected at the hub device.
摘要翻译： 一种用于提供具有增强的可靠性的级联互连存储器系统的集线器设备，存储器系统和方法。 集线器设备包括与高速总线的接口，用于与存储器控制器进行通信。 存储器控制器和集线器设备包括在级联互连存储器系统中，并且高速总线包括位通道和一个或多个时钟通道。 集线器设备还包括与存储器控制器通信并可由服务接口读取的双向故障信号线。 集线器设备还包括用于存储关于在集线器设备处检测到的故障的信息的故障隔离寄存器（FIR），该信息包括检测到的故障的严重性级别。 此外，集线器设备包括用于响应在集线器设备处检测到的故障的错误恢复逻辑。
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8.发明申请PROVIDING FRAME START INDICATION IN A MEMORY SYSTEM HAVING INDETERMINATE READ DATA LATENCY 有权在具有INDETERMINATE读取数据延迟的存储器系统中提供帧起始指示公开(公告)号：US20120151171A1
公开(公告)日：2012-06-14
申请号：US13397819
申请日：2012-02-16
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A memory system, having indeterminate read data latency, that includes a memory controller and one or more hub devices. The memory controller is configured for receiving data transfers via an upstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting a frame start indicator. The data frame includes an identification tag that is utilized by the memory controller to associate the data frame with a corresponding read instruction issued by the memory controller. The one or more hub devices are in communication with the memory controller in a cascade interconnect manner via the upstream channel and a downstream channel. Each hub device is configured for receiving the data transfers via the upstream channel or the downstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting the frame start indicator.
摘要翻译： 具有不确定的读取数据延迟的存储器系统，其包括存储器控制器和一个或多个集线器设备。 存储器控制器被配置为经由上游信道接收数据传输，并且通过检测帧起始指示符来确定数据传输的全部或一个子集是否包括数据帧。 数据帧包括由存储器控制器用于将数据帧与由存储器控制器发出的相应读取指令相关联的识别标签。 一个或多个集线器设备经由上游信道和下游信道以级联互连方式与存储器控制器通信。 每个集线器设备被配置用于经由上游信道或下游信道接收数据传输，并且用于通过检测帧起始指示符来确定数据传输的全部或一个子集是否包括数据帧。
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公开(公告)号：US20110320914A1
公开(公告)日：2011-12-29
申请号：US12822503
申请日：2010-06-24
申请人： Luiz C. Alves , Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Eldee Stephens
发明人： Luiz C. Alves , Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Eldee Stephens
IPC分类号： G06F11/10
CPC分类号： G06F11/1004 , G06F11/108
摘要： Error correction and detection in a redundant memory system that includes a memory controller; a plurality of memory channels in communication with the memory controller, the memory channels including a plurality of memory devices; a cyclical redundancy code (CRC) mechanism for detecting that one of the memory channels has failed, and for marking the memory channel as a failing memory channel; and an error correction code (ECC) mechanism. The ECC is configured for ignoring the marked memory channel and for detecting and correcting additional memory device failures on memory devices located on one or more of the other memory channels, thereby allowing the memory system to continue to run unimpaired in the presence of the memory channel failure.
摘要翻译： 在包括存储器控制器的冗余存储器系统中的错误校正和检测; 与存储器控制器通信的多个存储器通道，存储器通道包括多个存储器件; 用于检测存储器通道之一的循环冗余码（CRC）机制已经失败，并用于将存储器通道标记为故障存储器通道; 和纠错码（ECC）机制。 ECC被配置为忽略标记的存储器通道并且用于检测和校正位于一个或多个其它存储器通道上的存储器设备上的附加存储器件故障，从而允许存储器系统在存在存储器通道的情况下继续运行不受损害 失败。
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公开(公告)号：US20110320869A1
公开(公告)日：2011-12-29
申请号：US12822964
申请日：2010-06-24
申请人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
发明人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
CPC分类号： G06F11/1666 , G06F11/1044 , G06F11/108 , G06F11/141 , G06F11/1604 , G06F11/20 , G06F11/2007 , G06F2211/1088
摘要： Providing homogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for blocking off new operations from starting on the memory channels, for completing any pending operations on the memory channels, for performing a recovery operation on the memory channels and for starting the new operations on at least a first subset of the memory channels. The memory system is capable of operating with the first subset of the memory channels.
摘要翻译： 在包括存储器控制器，与存储器控制器通信的多个存储器通道，用于检测故障存储器通道的错误检测代码机构和错误恢复机制的冗余存储器系统中提供均匀恢复。 错误恢复机制被配置为用于接收故障存储器通道的通知，用于阻止新的操作在存储器通道上启动，以完成存储器通道上的任何未决操作，用于在存储器通道上执行恢复操作并启动 至少在存储器通道的第一子集上进行新的操作。 存储器系统能够与存储器通道的第一子集一起操作。
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