利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

172 条记录 (耗时 0.07 秒)

    Charge-trapping memory device and methods for operating and manufacturing the cell
    3.
    发明授权
    Charge-trapping memory device and methods for operating and manufacturing the cell 有权
    电荷捕获存储器件以及用于操作和制造电池的方法

    公开(公告)号：US07402490B2

    公开(公告)日：2008-07-22

    申请号：US11253939

    申请日：2005-10-19

    申请人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

    发明人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11568 ,  G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/7923

    摘要： To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.

    摘要翻译： 为了制造存储器件，在半导体本体上形成栅极电介质层，并且在栅极介电层上形成栅极电极层。 栅电极层被构造成形成具有侧壁的栅电极。 执行蚀刻处理以从栅极电极的相对侧上的栅电极下方去除栅极电介质层的部分。 边界层，例如氧化物层，形成在半导体本体的上表面上，栅电极的下表面邻近已经去除了栅极电介质，从而留下空间。 然后可以沉积电荷捕获层材料以填充空间。 然后在与栅电极相邻的半导体本体中形成源区和漏区。

    Charge-trapping memory device and methods for operating and manufacturing the cell
    4.
    发明申请
    Charge-trapping memory device and methods for operating and manufacturing the cell 有权
    电荷捕获存储器件以及用于操作和制造电池的方法

    公开(公告)号：US20060091448A1

    公开(公告)日：2006-05-04

    申请号：US11253939

    申请日：2005-10-19

    申请人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

    发明人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11568 ,  G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/7923

    摘要： To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.

    摘要翻译： 为了制造存储器件，在半导体本体上形成栅极电介质层，并且在栅极介电层上形成栅极电极层。 栅电极层被构造成形成具有侧壁的栅电极。 执行蚀刻处理以从栅极电极的相对侧上的栅电极下方去除栅极电介质层的部分。 边界层，例如氧化物层，形成在半导体本体的上表面上，栅电极的下表面邻近已经去除了栅极电介质，从而留下空间。 然后可以沉积电荷捕获层材料以填充空间。 然后在与栅电极相邻的半导体本体中形成源区和漏区。

    Multi-bit virtual-ground NAND memory device
    5.
    发明申请
    Multi-bit virtual-ground NAND memory device 有权
    多位虚拟NAND存储器件

    公开(公告)号：US20060245233A1

    公开(公告)日：2006-11-02

    申请号：US11119376

    申请日：2005-04-29

    申请人： Thomas Mikolajick ,  Josef Willer ,  Corvin Liaw

    发明人： Thomas Mikolajick ,  Josef Willer ,  Corvin Liaw

    IPC分类号： G11C17/00

    CPC分类号： G11C16/0483 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11568

    摘要： An array of charge-trapping multi-bit memory cells is arranged in a virtual-ground NAND architecture. The memory cells are erased by Fowler-Nordheim tunneling of electrons into the memory layers. The write operation is effected by hot hole injection. A write voltage is applied by a bitline to two NAND chains in series. The subsequent bitline on the side of the memory cell to be programmed is maintained on floating potential, whereas the bitline on the other side is set to an inhibit voltage, which is provided to inhibit a program disturb of an addressed memory cell which is not to be programmed. This virtual-ground NAND architecture of charge-trapping memory cells enables an increased storage density.

    摘要翻译： 一个电荷捕获多位存储单元的阵列被布置在虚拟地NAND架构中。 存储器单元被Fowler-Nordheim擦除，将电子隧穿到存储器层中。 写入操作通过热空穴注入来实现。 写入电压通过位线施加到两个串联的NAND链。 要编程的存储器单元侧的后续位线保持浮置电位，而另一侧的位线被设置为禁止电压，该禁止电压被提供以阻止寻址的存储器单元的程序干扰 被编程。 电荷俘获存储器单元的虚拟NAND架构能够提高存储密度。

    Multi-bit virtual-ground NAND memory device
    6.
    发明授权
    Multi-bit virtual-ground NAND memory device 有权
    多位虚拟NAND存储器件

    公开(公告)号：US07272040B2

    公开(公告)日：2007-09-18

    申请号：US11119376

    申请日：2005-04-29

    申请人： Thomas Mikolajick ,  Josef Willer ,  Corvin Liaw

    发明人： Thomas Mikolajick ,  Josef Willer ,  Corvin Liaw

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0483 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11568

    摘要： An array of charge-trapping multi-bit memory cells is arranged in a virtual-ground NAND architecture. The memory cells are erased by Fowler-Nordheim tunneling of electrons into the memory layers. The write operation is effected by hot hole injection. A write voltage is applied by a bitline to two NAND chains in series. The subsequent bitline on the side of the memory cell to be programmed is maintained on floating potential, whereas the bitline on the other side is set to an inhibit voltage, which is provided to inhibit a program disturb of an addressed memory cell which is not to be programmed. This virtual-ground NAND architecture of charge-trapping memory cells enables an increased storage density.

    摘要翻译： 一个电荷捕获多位存储单元的阵列被布置在虚拟地NAND架构中。 存储器单元被Fowler-Nordheim擦除，将电子隧穿到存储器层中。 写入操作通过热空穴注入来实现。 写入电压通过位线施加到两个串联的NAND链。 要编程的存储器单元侧的后续位线保持浮置电位，而另一侧的位线被设置为禁止电压，该禁止电压被提供以阻止寻址的存储器单元的程序干扰 被编程。 电荷俘获存储器单元的虚拟NAND架构能够提高存储密度。

    Integrated memory device and method for operating the same
    7.
    发明申请
    Integrated memory device and method for operating the same 有权
    集成存储器件及其操作方法

    公开(公告)号：US20060168505A1

    公开(公告)日：2006-07-27

    申请号：US11339846

    申请日：2006-01-26

    申请人： Corvin Liaw ,  Josef Willer

    发明人： Corvin Liaw ,  Josef Willer

    IPC分类号： H04L1/08 ,  H04L1/22 ,  H04L1/24

    CPC分类号： G11C13/0011 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2213/77 ,  H01L27/101

    摘要： A memory device includes an array of memory cells that include a memory element having a non-reactive resistance whose magnitude is programmable to assume a high-resistance state or a low-resistance state. Sets of first and second lines provide access to the memory cells, wherein the memory element of each memory cell is coupled between one of the first lines and one of the second lines. A checking unit determines whether to invert data values to be stored in memory cells coupled to at least a section of respective ones of the first lines based on a number of memory cells that would be programmed in the high-resistance state or the low-resistance state as a result of the data values in order to reduce the number memory cells programmed in the low-resistance state and the resulting leakage current.

    摘要翻译： 存储器件包括存储器单元阵列，其包括具有非反应电阻的存储元件，其大小可编程为呈现高电阻状态或低电阻状态。 第一和第二行的集合提供对存储器单元的访问，其中每个存储器单元的存储元件耦合在第一行之一和第二行中的一个之间。 检查单元基于将以高电阻状态编程的存储器单元的数量或低电阻来确定是否反转要存储在耦合到第一行中的相应的第一行的至少一部分的存储器单元中的数据值 作为数据值的结果，为了减少在低电阻状态下编程的存储单元数量和所产生的漏电流。

    Semiconductor memory device comprising memory cells with floating gate electrode and method of production
    8.
    发明申请
    Semiconductor memory device comprising memory cells with floating gate electrode and method of production 有权
    半导体存储器件包括具有浮栅电极的存储单元和制造方法

    公开(公告)号：US20060038220A1

    公开(公告)日：2006-02-23

    申请号：US10921766

    申请日：2004-08-19

    申请人： Karl-Heinz Kusters ,  Josef Willer ,  Corvin Liaw

    发明人： Karl-Heinz Kusters ,  Josef Willer ,  Corvin Liaw

    IPC分类号： H01L29/788

    CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/51 ,  H01L29/66825 ,  H01L29/792

    摘要： Transistor bodies of semiconductor material located at a main surface of a semiconductor substrate between shallow trench isolations are provided with a rounded or curved upper surface. A floating gate electrode is arranged above said upper surface and electrically insulated from the semiconductor material by a tunnel dielectric having essentially the same tiny thickness throughout a primary tunnel area encompassing the area of curvature. The floating gate electrode may bridge the transistor body and is covered with a coupling dielectric provided for a control gate electrode, which forms part of a wordline.

    摘要翻译： 位于浅沟槽隔离物之间的半导体衬底的主表面处的半导体材料的晶体管本体具有圆形或弯曲的上表面。 浮栅电极布置在所述上​​表面之上并且通过隧道电介质与半导体材料电绝缘，所述隧道电介质具有贯穿所述曲率区域的主隧道区域具有基本上相同的微小厚度。 浮栅电极可以桥接晶体管本体，并被形成为形成字线一部分的控制栅电极的耦合电介质覆盖。

    Integrated memory device and method for operating the same
    9.
    发明授权
    Integrated memory device and method for operating the same 有权
    集成存储器件及其操作方法

    公开(公告)号：US07280392B2

    公开(公告)日：2007-10-09

    申请号：US11339846

    申请日：2006-01-26

    申请人： Corvin Liaw ,  Josef Willer

    发明人： Corvin Liaw ,  Josef Willer

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0011 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2213/77 ,  H01L27/101

    摘要： A memory device includes an array of memory cells that include a memory element having a non-reactive resistance whose magnitude is programmable to assume a high-resistance state or a low-resistance state. Sets of first and second lines provide access to the memory cells, wherein the memory element of each memory cell is coupled between one of the first lines and one of the second lines. A checking unit determines whether to invert data values to be stored in memory cells coupled to at least a section of respective ones of the first lines based on a number of memory cells that would be programmed in the high-resistance state or the low-resistance state as a result of the data values in order to reduce the number memory cells programmed in the low-resistance state and the resulting leakage current.

    摘要翻译： 存储器件包括存储器单元阵列，其包括具有非反应电阻的存储元件，其大小可编程为呈现高电阻状态或低电阻状态。 第一和第二行的集合提供对存储器单元的访问，其中每个存储器单元的存储元件耦合在第一行之一和第二行中的一个之间。 检查单元基于将以高电阻状态编程的存储器单元的数量或低电阻来确定是否反转要存储在耦合到第一行中的相应的第一行的至少一部分的存储器单元中的数据值 作为数据值的结果，为了减少在低电阻状态下编程的存储单元数量和所产生的漏电流。

    Semiconductor memory device comprising memory cells with floating gate electrode and method of production
    10.
    发明授权
    Semiconductor memory device comprising memory cells with floating gate electrode and method of production 有权
    半导体存储器件包括具有浮栅电极的存储单元和制造方法

    公开(公告)号：US07250651B2

    公开(公告)日：2007-07-31

    申请号：US10921766

    申请日：2004-08-19

    申请人： Karl-Heinz Küsters ,  Josef Willer ,  Corvin Liaw

    发明人： Karl-Heinz Küsters ,  Josef Willer ,  Corvin Liaw

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L31/062

    CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/51 ,  H01L29/66825 ,  H01L29/792

    摘要： Transistor bodies of semiconductor material located at a main surface of a semiconductor substrate between shallow trench isolations are provided with a rounded or curved upper surface. A floating gate electrode is arranged above said upper surface and electrically insulated from the semiconductor material by a tunnel dielectric having essentially the same tiny thickness throughout a primary tunnel area encompassing the area of curvature. The floating gate electrode may bridge the transistor body and is covered with a coupling dielectric provided for a control gate electrode, which forms part of a wordline.

    摘要翻译： 位于浅沟槽隔离物之间的半导体衬底的主表面处的半导体材料的晶体管本体具有圆形或弯曲的上表面。 浮栅电极布置在所述上​​表面之上并且通过隧道电介质与半导体材料电绝缘，所述隧道电介质具有贯穿所述曲率区域的主隧道区域具有基本上相同的微小厚度。 浮栅电极可以桥接晶体管本体，并被形成为形成字线一部分的控制栅电极的耦合电介质覆盖。