公开(公告)号：US06909141B2

公开(公告)日：2005-06-21

申请号：US10047013

申请日：2002-01-16

申请人： Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Thomas Äugle ,  Herbert Schäfer ,  Martin Franosch

发明人： Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Thomas Äugle ,  Herbert Schäfer ,  Martin Franosch

IPC分类号： H01L21/335 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/76 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30 ,  H01L21/8238

CPC分类号： B82Y10/00 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/7613 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

摘要： A vertical semiconductor transistor component is built up on a substrate by using a statistical mask. The vertical semiconductor transistor component has vertical pillar structures statistically distributed over the substrate. The vertical pillar structures are electrically connected on a base side thereof to a first common electrical contact. The vertical pillar structures include, along the vertical direction, layer zones of differing conductivity, and have insulation layers on their circumferential walls. An electrically conductive material is deposited between the pillar structures and forms a second electrical contact of the semiconductor transistor component. The pillar structures are electrically contacted to a third common electrical contact on their capping side.

摘要翻译： 通过使用统计掩模在衬底上构建垂直半导体晶体管组件。 垂直半导体晶体管组件具有统计分布在衬底上的垂直柱结构。 垂直柱结构在其基极侧电连接到第一公共电接触。 垂直柱结构沿垂直方向包括不同导电性的层区，并且在其周壁上具有绝缘层。 导电材料沉积在柱结构之间并形成半导体晶体管组件的第二电接触。 支柱结构在其封盖侧与第三公共电触头电接触。

公开(公告)号：US06337247B1

公开(公告)日：2002-01-08

申请号：US09487411

申请日：2000-01-18

申请人： Thomas Schulz ,  Thomas Äugle ,  Wolfgang Rösner ,  Lothar Risch

发明人： Thomas Schulz ,  Thomas Äugle ,  Wolfgang Rösner ,  Lothar Risch

IPC分类号： H01L21336

CPC分类号： H01L29/66666 ,  H01L29/7827 ,  H01L29/7834

摘要： A spacer is used as a mask in an etching step during which a layer structure is produced for a channel layer and for a first source/drain region. After the layer structure has been produced, the first source/drain region and a second source/drain region can be produced by implantation. The second source/drain region is self-aligned on two mutually opposite flanks of the layer structure. A gate electrode can be produced in the form of a spacer on the two flanks. In order to avoid a capacitance formed by a first contact of the gate electrode and the first source/drain region, a part of the first source/drain region may be removed. If the layer structure is produced along edges of an inner area, then a third contact of the second source/drain region may be produced inside the inner area in order to reduce the surface area of the transistor.

摘要翻译： 在蚀刻步骤中使用间隔物作为掩模，在该步骤中，为沟道层和第一源极/漏极区域产生层结构。 在生成层结构之后，可以通过注入产生第一源极/漏极区域和第二源极/漏极区域。 第二源极/漏极区域在层结构的两个相互相对的侧面上自对准。 可以在两个侧面上以间隔物的形式制造栅电极。 为了避免由栅极电极和第一源极/漏极区域的第一接触形成的电容，可以去除第一源极/漏极区域的一部分。 如果沿着内部区域的边缘产生层结构，则可以在内部区域内产生第二源极/漏极区域的第三接触，以便减小晶体管的表面积。