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1.发明授权LDMOS transistors for CMOS technologies and an associated production method 有权用于CMOS技术的LDMOS晶体管和相关的生产方法公开(公告)号：US09224856B2
公开(公告)日：2015-12-29
申请号：US13635535
申请日：2011-04-07
申请人： Thomas Uhlig , Lutz Steinbeck
发明人： Thomas Uhlig , Lutz Steinbeck
IPC分类号： H01L29/78 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/66
CPC分类号： H01L29/7816 , H01L21/823814 , H01L27/092 , H01L29/0619 , H01L29/063 , H01L29/0649 , H01L29/0653 , H01L29/1095 , H01L29/665 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： In a semiconductor component or device, a lateral power effect transistor is produced as an LDMOS transistor in such a way that, in combination with a trench isolation region (12) and the heavily doped feed guiding region (28, 28A), an improved potential profile is achieved in the drain drift region (8) of the transistor. For this purpose, in advantageous embodiments, it is possible to use standard implantation processes of CMOS technology, without additional method steps being required.
摘要翻译： 在半导体部件或器件中，横向功率效应晶体管以与沟槽隔离区（12）和重掺杂进料引导区（28,28A）组合的方式产生为LDMOS晶体管，其具有改善的电位 在晶体管的漏极漂移区域（8）中实现。 为此，在有利的实施例中，可以使用CMOS技术的标准注入工艺，而不需要额外的方法步骤。
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2.发明申请LDMOS Transistors For CMOS Technologies And An Associated Production Method 有权用于CMOS技术的LDMOS晶体管及相关生产方法公开(公告)号：US20130175615A1
公开(公告)日：2013-07-11
申请号：US13635535
申请日：2011-04-07
申请人： Thomas Uhlig , Lutz Steinbeck
发明人： Thomas Uhlig , Lutz Steinbeck
CPC分类号： H01L29/7816 , H01L21/823814 , H01L27/092 , H01L29/0619 , H01L29/063 , H01L29/0649 , H01L29/0653 , H01L29/1095 , H01L29/665 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： In a semiconductor component or device, a lateral power effect transistor is produced as an LDMOS transistor in such a way that, in combination with a trench isolation region (12) and the heavily doped feed guiding region (28, 28A), an improved potential profile is achieved in the drain drift region (8) of the transistor. For this purpose, in advantageous embodiments, it is possible to use standard implantation processes of CMOS technology, without additional method steps being required.
摘要翻译： 在半导体部件或器件中，横向功率效应晶体管以与沟槽隔离区（12）和重掺杂进料引导区（28,28A）组合的方式产生为LDMOS晶体管，其具有改善的电位 在晶体管的漏极漂移区域（8）中实现。 为此，在有利的实施例中，可以使用CMOS技术的标准注入工艺，而不需要额外的方法步骤。
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公开(公告)号：US08633013B2
公开(公告)日：2014-01-21
申请号：US12451243
申请日：2008-05-05
申请人： Thomas Kaiser , Klaus-Peter Möbius , Torsten Schulz , Thomas Uhlig , Alexander Von Schenk Zu Schweinsberg , Eugen Ermantraut , Jens Tuchscheerer
发明人： Thomas Kaiser , Klaus-Peter Möbius , Torsten Schulz , Thomas Uhlig , Alexander Von Schenk Zu Schweinsberg , Eugen Ermantraut , Jens Tuchscheerer
IPC分类号： C12M1/34
CPC分类号： B01L3/50273 , B01L3/502715 , B01L3/502738 , B01L2300/0636 , B01L2300/0816 , B01L2300/123 , B01L2400/0481
摘要： A method for assaying a sample for each of multiple analytes is described. The method includes contacting an array of spaced-apart test zones with a liquid sample (e.g., whole blood). The test zones disposed within a channel of a microfluidic device. The channel is defined by at least one flexible wall and a second wall which may or may not be flexible. Each test zone comprising a probe compound specific for a respective target analyte. The microfluidic device is compressed to reduce the thickness of the channel, which is the distance between the inner surfaces of the walls within the channel. The presence of each analyte is determined by optically detecting an interaction at each of multiple test zones for which the distance between the inner surfaces at the corresponding location is reduced. The interaction at each test zone is indicative of the presence in the sample of a target analyte.
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公开(公告)号：US08222679B2
公开(公告)日：2012-07-17
申请号：US12593493
申请日：2008-03-26
IPC分类号： H01L29/66
CPC分类号： H01L27/22 , G01R33/07 , H01L43/065
摘要： A semiconductor device with an integrated circuit on a semiconductor substrate comprises a Hall effect sensor in a first active region and a lateral high voltage MOS transistor in a second active region. The semiconductor device of the present invention is characterized in that the structure of the integrated Hall effect sensor is strongly related with the structure of a high-voltage DMOS transistor. The integrated Hall effect sensor is in some features similar to a per se known high-voltage DMOS transistor having a double RESURF structure. The control contacts of the Hall effect sensor correspond to the source and drain contacts of the high-voltage DMOS transistor. The semiconductor device of the present invention allows a simplification of the process integration.
摘要翻译： 在半导体衬底上具有集成电路的半导体器件包括第一有源区中的霍尔效应传感器和第二有源区中的横向高压MOS晶体管。 本发明的半导体器件的特征在于，集成霍尔效应传感器的结构与高电压DMOS晶体管的结构密切相关。 集成的霍尔效应传感器具有与本身已知的具有双重RESURF结构的已知高压DMOS晶体管相似的特征。 霍尔效应传感器的控制触点对应于高压DMOS晶体管的源极和漏极触点。 本发明的半导体器件允许简化工艺集成。
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公开(公告)号：US20110127583A1
公开(公告)日：2011-06-02
申请号：US12593493
申请日：2008-03-26
IPC分类号： H01L27/22
CPC分类号： H01L27/22 , G01R33/07 , H01L43/065
摘要： A semiconductor device with an integrated circuit on a semiconductor substrate comprises a Hall effect sensor in a first active region and a lateral high voltage MOS transistor in a second active region. The semiconductor device of the present invention is characterized in that the structure of the integrated Hall effect sensor is strongly related with the structure of a high-voltage DMOS transistor. The integrated Hall effect sensor is in some features similar to a per se known high-voltage DMOS transistor having a double RESURF structure. The control contacts of the Hall effect sensor correspond to the source and drain contacts of the high-voltage DMOS transistor. The semiconductor device of the present invention allows a simplification of the process integration.
摘要翻译： 在半导体衬底上具有集成电路的半导体器件包括第一有源区中的霍尔效应传感器和第二有源区中的横向高压MOS晶体管。 本发明的半导体器件的特征在于，集成霍尔效应传感器的结构与高电压DMOS晶体管的结构密切相关。 集成的霍尔效应传感器具有与本身已知的具有双重RESURF结构的已知高压DMOS晶体管相似的特征。 霍尔效应传感器的控制触点对应于高压DMOS晶体管的源极和漏极触点。 本发明的半导体器件允许简化工艺集成。
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6.发明申请MASK-SAVING PRODUCTION OF COMPLEMENTARY LATERAL HIGH-VOLTAGE TRANSISTORS WITH A RESURF STRUCTURE 有权具有RESURF结构的补充型横向高压晶体管的生产公开(公告)号：US20100311214A1
公开(公告)日：2010-12-09
申请号：US12593310
申请日：2008-03-26
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L27/0922
摘要： The invention relates to a method for the production of a first lateral high-voltage MOS transistor and a second lateral high-voltage MOS transistor complimentary thereto on a substrate, wherein the first and second lateral high-voltage MOS transistors each have a conductivity type opposite a drift region, comprising the steps of providing a substrate of a first conductivity type comprising a first active region for the first lateral high-voltage MOS transistor and a second active region for the second lateral high-voltage MOS transistor, and the producing at least one first doping region of the first conductivity type in the first active region and, on the other hand, in the second active region, a drain extension region of the first conductivity type extending from the substrate surface to the interior of the substrate, which allows a simultaneous implantation of doping material in the first and second active regions through respective mask openings of one and the same mask.
摘要翻译： 本发明涉及一种在衬底上制造第一横向高压MOS晶体管和与之互补的第二横向高压MOS晶体管的方法，其中第一和第二横向高压MOS晶体管各自具有相反的导电类型 漂移区域，包括以下步骤：提供包括第一横向高压MOS晶体管的第一有源区和第二横向高压MOS晶体管的第二有源区的第一导电类型的衬底，并且至少产生 第一有源区中第一导电类型的第一掺杂区域和第二有源区中的第一导电类型的漏极延伸区域从衬底表面延伸到衬底的内部，这允许 通过相同掩模的相应掩模开口同时将掺杂材料注入第一和第二有源区域。
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公开(公告)号：US20100056387A1
公开(公告)日：2010-03-04
申请号：US12516070
申请日：2007-11-22
申请人： Torsten Schulz , Thomas Kaiser , Thomas Uhlig , Klaus Peter Moubius , Alexander Von Schenk Zu Schweinsberg
发明人： Torsten Schulz , Thomas Kaiser , Thomas Uhlig , Klaus Peter Moubius , Alexander Von Schenk Zu Schweinsberg
CPC分类号： G01N33/54386 , B01L3/5027 , B01L2300/0636 , B01L2300/0654 , B01L2300/0825 , B01L2400/0406 , B01L2400/0481 , Y10T436/2575
摘要： A method for assaying a sample for each of multiple analytes is described. The method includes contacting an array of spaced-apart test zones with a liquid sample (e.g., whole blood). The test zones are disposed within a channel of a microfluidic device. The channel is defined by at least one flexible wall and a second wall which may or may not be flexible. Each test zone comprising a probe compound specific for a respective target analyte. The microfluidic device is compressed to reduce the thickness of the channel, which is the distance between the inner surfaces of the walls within the channel. The presence of each analyte is determined by optically detecting an interaction at each of multiple test zones for which the distance between the inner surfaces at the corresponding location is reduced. The interaction at each test zone is indicative of the presence in the sample of a target analyte.
摘要翻译： 描述了用于分析多种分析物中的每一种的样品的方法。 该方法包括使间隔开的测试区域的阵列与液体样品（例如全血）接触。 测试区域设置在微流体装置的通道内。 通道由至少一个柔性壁和可以是柔性的第二壁限定。 每个测试区域包含对各个目标分析物特异的探针化合物。 微流体装置被压缩以减小通道的厚度，其是通道内的壁的内表面之间的距离。 每个分析物的存在通过光学检测在相应位置处的内表面之间的距离减小的多个测试区域中的每一个处的相互作用来确定。 每个测试区域的相互作用表明样品中目标分析物的存在。
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公开(公告)号：US08349616B2
公开(公告)日：2013-01-08
申请号：US12516070
申请日：2007-11-22
申请人： Torsten Schulz , Thomas Kaiser , Thomas Uhlig , Klaus Peter Möbius , Alexander Von Schenk Zu Schweinsberg
发明人： Torsten Schulz , Thomas Kaiser , Thomas Uhlig , Klaus Peter Möbius , Alexander Von Schenk Zu Schweinsberg
IPC分类号： G01N21/00
CPC分类号： G01N33/54386 , B01L3/5027 , B01L2300/0636 , B01L2300/0654 , B01L2300/0825 , B01L2400/0406 , B01L2400/0481 , Y10T436/2575
摘要： A method for assaying a sample for each of multiple analysis is described. The method includes contacting an array of spaced-apart test zones with a liquid sample (e.g., whole blood). The test zones are disposed within a channel of a microfluidic device. The channel is defined by at least one flexible wall and a second wall which may or may not be flexible. Each test zone includes a probe compound specific for a respective target analyte. The microfluidic device is compressed to reduce the thickness of the channel, which is the distance between the inner surfaces of the walls within the channel. The presence of each analyte is determined by optically detecting an interaction at each of multiple zones for which the distance between the inner surfaces at the corresponding location is reduced. The interaction at each test zone is indicative of the presence in the sample of a target analyte.
摘要翻译： 描述了用于分析多个分析中的每一个的样品的方法。 该方法包括使间隔开的测试区域的阵列与液体样品（例如全血）接触。 测试区域设置在微流体装置的通道内。 通道由至少一个柔性壁和可以是柔性的第二壁限定。 每个测试区域包括对各个目标分析物特异的探针化合物。 微流体装置被压缩以减小通道的厚度，其是通道内的壁的内表面之间的距离。 每个分析物的存在通过光学检测在相应位置处的内表面之间的距离减小的多个区域中的相互作用来确定。 每个测试区域的相互作用表明样品中目标分析物的存在。
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公开(公告)号：US07841151B2
公开(公告)日：2010-11-30
申请号：US12008945
申请日：2008-01-15
申请人： Thomas Uhlig
发明人： Thomas Uhlig
IPC分类号： E04C2/38
CPC分类号： A47G27/0431 , E04F19/061 , Y10S52/13 , Y10T24/27 , Y10T428/195
摘要： An edge molding providing an edging for a floor covering such as a carpet, rug, tile and the like floor coverings comprising a stepped-molding which attaches to a subfloor edge through a hook and loop means to provide an edge molding for a floor covering which floor covering is attached to the subfloor through a means of a hook and loop arrangement.
摘要翻译： 提供用于诸如地毯，地毯，瓷砖和类似地板覆盖物的地板覆盖物的边缘成型件，其包括阶梯式模制件，其通过钩环装置附接到底部地板边缘，以提供用于地板覆盖物的边缘成型 地板覆盖物通过钩环布置的方式附接到底层地板。
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公开(公告)号：US20100148255A1
公开(公告)日：2010-06-17
申请号：US12593309
申请日：2008-03-26
CPC分类号： H01L29/0634 , H01L29/7816 , H01L29/7835
摘要： For achieving an enhanced combination of a low on-resistance at a high break-through voltage a lateral high-voltage MOS transistor comprises a plurality of doped RESURF regions of the first conductivity type within the drift region, wherein the doped RESURF regions are separated from each other by drift region sections in a first lateral direction (y), which is parallel to a substrate surface and is orthogonal to a connecting line from the source region to the drain region, and also in a depth direction, which is orthogonal to the substrate surface, such that in each of said two directions an alternating arrangement of regions of the first and second conductivity types is provided.
摘要翻译： 为了在高突变电压下实现低导通电阻的增强组合，横向高压MOS晶体管包括在漂移区内的第一导电类型的多个掺杂RESURF区域，其中掺杂的RESURF区域与 彼此相对于第一横向方向（y）的漂移区域，其平行于基板表面并且与从源极区域到漏极区域的连接线垂直，并且还与深度方向垂直，该深度方向与 使得在所述两个方向中的每一个中提供所述第一和第二导电类型的区域的交替布置。
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