公开(公告)号：US07446036B1

公开(公告)日：2008-11-04

申请号：US11958691

申请日：2007-12-18

申请人： Tibor Bolom ,  Stephan Grunow ,  David Rath ,  Andrew Herbert Simon

发明人： Tibor Bolom ,  Stephan Grunow ,  David Rath ,  Andrew Herbert Simon

IPC分类号： H01L21/4763 ,  H01L21/461

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids.

摘要翻译： 微电子结构和制造微电子结构的方法使用位于第一导体层上并形成的介电层。 孔通过介电层定位。 孔径垂直地穿入第一导体层，并且在电介质层下方的第一导体层内横向延伸，而不到达电介质层，以形成延伸和有翅的孔。 可以使用不存在空隙的电镀方法，将连续的通孔和互连件形成为锚固到延伸和有翼的孔中。

公开(公告)号：US07985928B2

公开(公告)日：2011-07-26

申请号：US12190814

申请日：2008-08-13

申请人： Tibor Bolom ,  Stephan Grunow ,  David L. Rath ,  Andrew Herbert Simon

发明人： Tibor Bolom ,  Stephan Grunow ,  David L. Rath ,  Andrew Herbert Simon

IPC分类号： H05K1/11

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids.

摘要翻译： 微电子结构和制造微电子结构的方法使用位于第一导体层上并形成的介电层。 孔通过介电层定位。 孔径垂直地穿入第一导体层，并且在电介质层下方的第一导体层内横向延伸，而不到达电介质层，以形成延伸和有翅的孔。 可以使用不存在空隙的电镀方法，将连续的通孔和互连件形成为锚固到延伸和有翼的孔中。

公开(公告)号：US20090151981A1

公开(公告)日：2009-06-18

申请号：US12190814

申请日：2008-08-13

申请人： Tibor Bolom ,  Stephan Grunow ,  David L. Rath ,  Andrew Herbert Simon

发明人： Tibor Bolom ,  Stephan Grunow ,  David L. Rath ,  Andrew Herbert Simon

IPC分类号： H01B5/14

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids

摘要翻译： 微电子结构和制造微电子结构的方法使用位于第一导体层上并形成的介电层。 孔通过介电层定位。 孔径垂直地穿入第一导体层，并且在电介质层下方的第一导体层内横向延伸，而不到达电介质层，以形成延伸和有翅的孔。 可以使用不存在空隙的电镀方法，将连续的通孔和互连件形成为锚固到延伸和有翼的孔中

公开(公告)号：US07671362B2

公开(公告)日：2010-03-02

申请号：US11953568

申请日：2007-12-10

申请人： Tibor Bolom ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Paul S. McLaughlin ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert ,  James Werking

发明人： Tibor Bolom ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Paul S. McLaughlin ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert ,  James Werking

IPC分类号： H01L23/58

CPC分类号： H01L22/12 ,  H01L22/34

摘要： A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.

摘要翻译： 集成电路（IC）器件制造的测试结构包括形成在IC晶片的各个区域的多个测试结构链，所述多个测试结构链中的每一个包括一个或多个通孔; 所述一个或多个通孔中的每一个与设置在其上的导电线接触，所述导电线被配置为使得其至少一个尺寸从链到链变化，从而在种子层和衬层层厚度之间产生从链到链的变化， 相同的沉积工艺条件。

公开(公告)号：US20090146143A1

公开(公告)日：2009-06-11

申请号：US11953568

申请日：2007-12-10

申请人： Tibor Bolom ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Paul S. McLaughlin ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert ,  James Werking

发明人： Tibor Bolom ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Paul S. McLaughlin ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert ,  James Werking

IPC分类号： H01L23/58 ,  H01L21/4763

CPC分类号： H01L22/12 ,  H01L22/34

摘要： A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.

摘要翻译： 集成电路（IC）器件制造的测试结构包括形成在IC晶片的各个区域的多个测试结构链，所述多个测试结构链中的每一个包括一个或多个通孔; 所述一个或多个通孔中的每一个与设置在其上的导电线接触，所述导电线被配置为使得其至少一个尺寸从链到链变化，从而在种子层和衬层层厚度之间产生从链到链的变化， 相同的沉积工艺条件。

公开(公告)号：US08105942B2

公开(公告)日：2012-01-31

申请号：US12763550

申请日：2010-04-20

申请人： Jihong Choi ,  Tibor Bolom

发明人： Jihong Choi ,  Tibor Bolom

IPC分类号： H01L21/4763

CPC分类号： H01L21/76814 ,  H01L21/31053 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved metal interconnect is formed with reduced metal voids and dendrites. An embodiment includes forming a mask layer on a dielectric layer, forming openings in the mask and dielectric layers, depositing a planarization layer over the mask layer and filling the openings, planarizing to remove the mask layer, removing the planarization layer from the openings, and filling the openings with metal. The planarization step prior to depositing the metal removes the etch undercut that occurs during formation of the openings and reduces the aspect ratio in the openings, thereby improving metal fill uniformity.

摘要翻译： 改进的金属互连形成有减少的金属空隙和枝晶。 一个实施例包括在电介质层上形成掩模层，在掩模和电介质层中形成开口，在掩模层上沉积平坦化层并填充开口，平坦化以去除掩模层，从开口去除平坦化层，以及 用金属填充开口。 在沉积金属之前的平坦化步骤去除了在形成开口期间发生的蚀刻底切，并且减小了开口中的纵横比，从而改善了金属填充均匀性。

公开(公告)号：US20110254139A1

公开(公告)日：2011-10-20

申请号：US12763550

申请日：2010-04-20

申请人： Jihong Choi ,  Tibor Bolom

发明人： Jihong Choi ,  Tibor Bolom

IPC分类号： H01L23/535 ,  H01L23/58 ,  H01L21/441

CPC分类号： H01L21/76814 ,  H01L21/31053 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved metal interconnect is formed with reduced metal voids and dendrites. An embodiment includes forming a mask layer on a dielectric layer, forming openings in the mask and dielectric layers, depositing a planarization layer over the mask layer and filling the openings, planarizing to remove the mask layer, removing the planarization layer from the openings, and filling the openings with metal. The planarization step prior to depositing the metal removes the etch undercut that occurs during formation of the openings and reduces the aspect ratio in the openings, thereby improving metal fill uniformity.

摘要翻译： 改进的金属互连形成有减少的金属空隙和枝晶。 一个实施例包括在电介质层上形成掩模层，在掩模和电介质层中形成开口，在掩模层上沉积平坦化层并填充开口，平坦化以去除掩模层，从开口去除平坦化层，以及 用金属填充开口。 在沉积金属之前的平坦化步骤去除了在形成开口期间发生的蚀刻底切，并且减小了开口中的纵横比，从而改善了金属填充均匀性。

公开(公告)号：US09059176B2

公开(公告)日：2015-06-16

申请号：US13451947

申请日：2012-04-20

申请人： Frieder Hainrich Baumann ,  Chao-Kun Hu ,  Andrew H. Simon ,  Tibor Bolom ,  Koichi Motoyama ,  Chengyu Charles Niu

发明人： Frieder Hainrich Baumann ,  Chao-Kun Hu ,  Andrew H. Simon ,  Tibor Bolom ,  Koichi Motoyama ,  Chengyu Charles Niu

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.

摘要翻译： 具有位于邻近侧壁的扩散阻挡层的结构和在介电材料层中蚀刻的开口的底部。 该结构还具有直接位于扩散阻挡层顶部的金属衬垫，直接位于金属衬垫顶部上的种子层，其中种子层由包括铜的材料制成，铜材料直接位于种子顶部 层，直接位于铜材料的顶部和选择性上的金属盖，以及直接位于金属盖的顶部并且邻近金属盖的封盖层。

公开(公告)号：US20130277842A1

公开(公告)日：2013-10-24

申请号：US13451947

申请日：2012-04-20

申请人： Frieder Hainrich Baumann ,  Chao-Kun Hu ,  Andrew H. Simon ,  Tibor Bolom ,  Koichi Motoyama ,  Chengyu Charles Niu

发明人： Frieder Hainrich Baumann ,  Chao-Kun Hu ,  Andrew H. Simon ,  Tibor Bolom ,  Koichi Motoyama ,  Chengyu Charles Niu

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.

公开(公告)号：US07329599B1

公开(公告)日：2008-02-12

申请号：US11082618

申请日：2005-03-16

申请人： Frank Wirbeleit ,  Tibor Bolom ,  Johannes Van Meer

发明人： Frank Wirbeleit ,  Tibor Bolom ,  Johannes Van Meer

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/265 ,  H01L21/76859 ,  H01L23/485 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods are provided for semiconductor devices having low contact resistance. The method in accordance with one embodiment of the invention comprises forming an insulating layer overlying a semiconductor substrate, the semiconductor substrate having a device region therein. An opening is formed through the insulating layer to expose a portion of the device region, and the portion of the device region is then electrically contacted by a metallic liner layer. To reduce the resistance of the liner layer and hence the contact, ions of a conductivity determining impurity are implanted into the metallic liner layer. A metal layer is then deposited overlying the metallic liner layer to fill the opening through the insulating layer and to form a conductive plug.

摘要翻译： 提供了具有低接触电阻的半导体器件的方法。 根据本发明的一个实施例的方法包括形成覆盖半导体衬底的绝缘层，其中半导体衬底具有器件区域。 通过绝缘层形成开口以暴露器件区域的一部分，并且器件区域的该部分然后被金属衬垫层电接触。 为了降低衬垫层的电阻并因此降低接触，导电性确定杂质的离子注入到金属衬垫层中。 然后将金属层沉积在金属衬垫层上方以通过绝缘层填充开口并形成导电插塞。