公开(公告)号：US07985928B2

公开(公告)日：2011-07-26

申请号：US12190814

申请日：2008-08-13

申请人： Tibor Bolom ,  Stephan Grunow ,  David L. Rath ,  Andrew Herbert Simon

发明人： Tibor Bolom ,  Stephan Grunow ,  David L. Rath ,  Andrew Herbert Simon

IPC分类号： H05K1/11

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids.

摘要翻译： 微电子结构和制造微电子结构的方法使用位于第一导体层上并形成的介电层。 孔通过介电层定位。 孔径垂直地穿入第一导体层，并且在电介质层下方的第一导体层内横向延伸，而不到达电介质层，以形成延伸和有翅的孔。 可以使用不存在空隙的电镀方法，将连续的通孔和互连件形成为锚固到延伸和有翼的孔中。

公开(公告)号：US20090151981A1

公开(公告)日：2009-06-18

申请号：US12190814

申请日：2008-08-13

申请人： Tibor Bolom ,  Stephan Grunow ,  David L. Rath ,  Andrew Herbert Simon

发明人： Tibor Bolom ,  Stephan Grunow ,  David L. Rath ,  Andrew Herbert Simon

IPC分类号： H01B5/14

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids

摘要翻译： 微电子结构和制造微电子结构的方法使用位于第一导体层上并形成的介电层。 孔通过介电层定位。 孔径垂直地穿入第一导体层，并且在电介质层下方的第一导体层内横向延伸，而不到达电介质层，以形成延伸和有翅的孔。 可以使用不存在空隙的电镀方法，将连续的通孔和互连件形成为锚固到延伸和有翼的孔中

公开(公告)号：US08298948B2

公开(公告)日：2012-10-30

申请号：US12613551

申请日：2009-11-06

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  David L. Rath ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  David L. Rath ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang

IPC分类号： H01L21/44 ,  H01L21/302

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76865 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for capping lines includes forming a metal film layer on a copper line by a selective deposition process, the copper line disposed in a dielectric substrate, wherein the depositing also results in the deposition of stray metal material on the surface of the dielectric substrate, and etching with an isotropic etching process to remove a portion of the metal film layer and the stray metal material on the surface of the dielectric substrate, wherein the metal film layer is deposited at an initial thickness sufficient to leave a metal film layer cap remaining on the copper line following the removal of the stray metal material.

摘要翻译： 一种封盖线的方法包括通过选择性沉积工艺在铜线上形成金属膜层，铜线设置在电介质基底中，其中沉积还导致杂散金属材料沉积在介质基片的表面上， 并用各向同性蚀刻工艺进行蚀刻以除去电介质基底表面上的金属膜层和杂散金属材料的一部分，其中金属膜层以足以使金属膜层盖保持在其上的初始厚度沉积 铜线除去杂散金属材料。

公开(公告)号：US20110108990A1

公开(公告)日：2011-05-12

申请号：US12613551

申请日：2009-11-06

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  David L. Rath ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert ,  Chih-Chao Yang

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  David L. Rath ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert ,  Chih-Chao Yang

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76865 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for capping lines includes forming a metal film layer on a copper line by a selective deposition process, the copper line disposed in a dielectric substrate, wherein the depositing also results in the deposition of stray metal material on the surface of the dielectric substrate, and etching with an isotropic etching process to remove a portion of the metal film layer and the stray metal material on the surface of the dielectric substrate, wherein the metal film layer is deposited at an initial thickness sufficient to leave a metal film layer cap remaining on the copper line following the removal of the stray metal material.

摘要翻译： 一种封盖线的方法包括通过选择性沉积工艺在铜线上形成金属膜层，铜线设置在电介质基底中，其中沉积还导致杂散金属材料沉积在介质基片的表面上， 并用各向同性蚀刻工艺进行蚀刻以除去电介质基底表面上的金属膜层和杂散金属材料的一部分，其中金属膜层以足以使金属膜层盖保持在其上的初始厚度沉积 铜线除去杂散金属材料。

公开(公告)号：US07517736B2

公开(公告)日：2009-04-14

申请号：US11307642

申请日：2006-02-15

申请人： Sanjay C. Mehta ,  Daniel C. Edelstein ,  John A. Fitzsimmons ,  Stephan Grunow ,  Henry A. Nye, III ,  David L. Rath

发明人： Sanjay C. Mehta ,  Daniel C. Edelstein ,  John A. Fitzsimmons ,  Stephan Grunow ,  Henry A. Nye, III ,  David L. Rath

IPC分类号： H01L21/82 ,  H01L21/4763

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are provided that enable the ability to use a less aggressive liner processes, while producing structures known to give a desired high stress migration and electro-migration reliability. The present invention circumvents the issue of sputter damage of low k (on the order of 3.2 or less) dielectric by creating the via “anchors” (interlocked and interpenetrated vias) through chemical means. This allows the elimination or significant reduction of the sputter-etching process used to create the via penetration (“drilling, gouging”) into the line below in the barrier/seed metallization step. The present invention achieves the above, while maintaining a reliable copper fill and device structure.

摘要翻译： 提供了使得能够使用较不积极的衬里工艺的能力，同时产生已知具有期望的高应力迁移和电迁移可靠性的结构。 本发明通过化学方法制造通孔“锚”（互锁和相互穿透的通孔）来规避低k（约3.2以下）电介质的溅射损伤问题。 这允许在阻挡/种子金属化步骤中消除或显着减少用于在下面的线中产生通孔穿透（“钻孔，气刨”）的溅射蚀刻工艺。 本发明实现上述，同时保持可靠的铜填充和装置结构。

公开(公告)号：US08617689B2

公开(公告)日：2013-12-31

申请号：US13443418

申请日：2012-04-10

申请人： Kuan-Neng Chen ,  Bruce K. Furman ,  Sampath Purushothaman ,  David L. Rath ,  Anna W. Topol ,  Cornelia K. Tsang

发明人： Kuan-Neng Chen ,  Bruce K. Furman ,  Sampath Purushothaman ,  David L. Rath ,  Anna W. Topol ,  Cornelia K. Tsang

IPC分类号： B32B3/00 ,  B32B15/04

CPC分类号： H01L24/05 ,  B23K20/023 ,  B23K20/233 ,  B23K20/24 ,  B23K2101/42 ,  H01L24/03 ,  H01L24/08 ,  H01L24/12 ,  H01L24/80 ,  H01L2224/0381 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/80203 ,  H01L2224/80345 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/80986 ,  H01L2924/14 ,  H01L2924/1461 ,  Y10T428/24479 ,  Y10T428/24521 ,  Y10T428/24545 ,  Y10T428/24612 ,  Y10T428/31678 ,  H01L2924/00012 ,  H01L2924/0001 ,  H01L2924/00

摘要： Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric, as well as related structures, are disclosed. One method includes providing a first substrate having a metal-dielectric pattern on a surface thereof; providing a second substrate having a metal-dielectric pattern on a surface thereof; performing a process resulting in the metal being raised above the dielectric; cleaning the metal; and bonding the first substrate to the second substrate. A related structure is also disclosed. The bonding of raised metal provides a strong bonding medium, and good electrical and thermal connections enabling creation of three dimensional integrated structures with enhanced functionality.

摘要翻译： 公开了包括金属电介质图案在表面上与在电介质上方凸起的金属以及相关结构的接合。 一种方法包括在其表面上提供具有金属 - 电介质图案的第一基板; 提供在其表面上具有金属 - 电介质图案的第二基板; 执行导致金属在电介质上方升高的过程; 清洗金属; 以及将所述第一基板接合到所述第二基板。 还公开了相关的结构。 凸起金属的结合提供了强大的粘合介质，以及良好的电气和热连接，能够创建具有增强功能的三维集成结构。

公开(公告)号：US08492239B2

公开(公告)日：2013-07-23

申请号：US13602957

申请日：2012-09-04

申请人： Robert L. Bruce ,  Geraud Jean-Michel Dubois ,  Theo J. Frot ,  Teddie P. Magbitang ,  Sampath Purushothaman ,  David L. Rath ,  Willi Volksen

发明人： Robert L. Bruce ,  Geraud Jean-Michel Dubois ,  Theo J. Frot ,  Teddie P. Magbitang ,  Sampath Purushothaman ,  David L. Rath ,  Willi Volksen

IPC分类号： H01L21/76

CPC分类号： H01L21/3105 ,  H01L21/02203 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76828

摘要： In one exemplary embodiment, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a plurality of pores; applying a filling material to an exposed surface of the first layer; heating the structure to a first temperature to enable the filling material to homogeneously fill the plurality of pores; after filling the plurality of pores, performing at least one first process on the structure; after performing the at least one first process, removing the filling material from the plurality of pores by heating the structure to a second temperature to decompose the filling material; and after removing the filling material from the plurality of pores, performing at least one second process on the structure, where the at least one second process is performed at a third temperature that is greater than the second temperature.

摘要翻译： 在一个示例性实施例中，一种方法包括：提供具有覆盖衬底的第一层的结构，其中第一层包括具有多个孔的电介质材料; 将填充材料施加到第一层的暴露表面; 将结构加热到第一温度以使填充材料均匀地填充多个孔; 在填充所述多个孔之后，在所述结构上执行至少一个第一处理; 在执行所述至少一个第一处理之后，通过将所述结构加热至第二温度以分解所述填充材料，从所述多个孔中除去所述填充材料; 并且在从所述多个孔中除去所述填充材料之后，对所述结构执行至少一个第二工艺，其中所述至少一个第二工艺在大于所述第二温度的第三温度下进行。

公开(公告)号：US20120329273A1

公开(公告)日：2012-12-27

申请号：US13602957

申请日：2012-09-04

申请人： Robert L. Bruce ,  Geraud Jean-Michel Dubois ,  Theo J. Frot ,  Teddie P. Magbitang ,  Sampath Purushothaman ,  David L. Rath ,  Willi Volksen

发明人： Robert L. Bruce ,  Geraud Jean-Michel Dubois ,  Theo J. Frot ,  Teddie P. Magbitang ,  Sampath Purushothaman ,  David L. Rath ,  Willi Volksen

IPC分类号： H01L21/28

CPC分类号： H01L21/3105 ,  H01L21/02203 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76828

摘要： In one exemplary embodiment, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a plurality of pores; applying a filling material to an exposed surface of the first layer; heating the structure to a first temperature to enable the filling material to homogeneously fill the plurality of pores; after filling the plurality of pores, performing at least one first process on the structure; after performing the at least one first process, removing the filling material from the plurality of pores by heating the structure to a second temperature to decompose the filling material; and after removing the filling material from the plurality of pores, performing at least one second process on the structure, where the at least one second process is performed at a third temperature that is greater than the second temperature.

摘要翻译： 在一个示例性实施例中，一种方法包括：提供具有覆盖衬底的第一层的结构，其中第一层包括具有多个孔的电介质材料; 将填充材料施加到第一层的暴露表面; 将结构加热到第一温度以使填充材料均匀地填充多个孔; 在填充所述多个孔之后，在所述结构上执行至少一个第一处理; 在执行所述至少一个第一处理之后，通过将所述结构加热至第二温度以分解所述填充材料，从所述多个孔中除去所述填充材料; 并且在从所述多个孔中除去所述填充材料之后，对所述结构进行至少一个第二工艺，其中所述至少一个第二工艺在大于所述第二温度的第三温度下进行。

公开(公告)号：US20110092067A1

公开(公告)日：2011-04-21

申请号：US12972808

申请日：2010-12-20

申请人： Griselda Bonilla ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang

发明人： Griselda Bonilla ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L23/5222 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask and the low-k material layer therebelow are etched to form cavities. A conductive material is plated on exposed metallic surfaces including portions of top surfaces of the metal feature to form metal pads. Metal silicide pads are formed by exposure of the metal pads to a silicon containing gas. An etch is performed to enlarge and merge the cavities in the low-k material layer. The metal feature is protected from the etch by the metal silicide pads. An interconnect structure having an air gap and free of defects to surfaces of the metal feature is formed.

摘要翻译： 在包括低k材料层和嵌入其中的金属特征的互连结构上形成硬掩模。 将嵌段聚合物施加到硬掩模层上，自组装和图案化以形成聚合物嵌段组分的聚合物基质并且包含圆柱形孔。 蚀刻硬掩模和低k材料层以形成空腔。 导电材料镀在暴露的金属表面上，包括金属特征的顶表面的部分以形成金属垫。 金属硅化物焊盘通过将金属焊盘暴露于含硅气体而形成。 进行蚀刻以放大和合并低k材料层中的空腔。 通过金属硅化物焊盘防止金属特征被蚀刻。 形成具有空隙并且没有金属特征表面的缺陷的互连结构。

公开(公告)号：US07884477B2

公开(公告)日：2011-02-08

申请号：US11949189

申请日：2007-12-03

申请人： Griselda Bonilla ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang

发明人： Griselda Bonilla ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5222 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask and the low-k material layer therebelow are etched to form cavities. A conductive material is plated on exposed metallic surfaces including portions of top surfaces of the metal feature to form metal pads. Metal silicide pads are formed by exposure of the metal pads to a silicon containing gas. An etch is performed to enlarge and merge the cavities in the low-k material layer. The metal feature is protected from the etch by the metal silicide pads. An interconnect structure having an air gap and free of defects to surfaces of the metal feature is formed.

摘要翻译： 在包括低k材料层和嵌入其中的金属特征的互连结构上形成硬掩模。 将嵌段聚合物施加到硬掩模层上，自组装和图案化以形成聚合物嵌段组分的聚合物基质并且包含圆柱形孔。 蚀刻硬掩模和低k材料层以形成空腔。 导电材料镀在暴露的金属表面上，包括金属特征的顶表面的部分以形成金属垫。 金属硅化物焊盘通过将金属焊盘暴露于含硅气体而形成。 进行蚀刻以放大和合并低k材料层中的空腔。 通过金属硅化物焊盘防止金属特征被蚀刻。 形成具有空隙并且没有金属特征表面的缺陷的互连结构。