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    Clock frequency doubler method and apparatus for serial flash testing
    1.
    发明申请
    Clock frequency doubler method and apparatus for serial flash testing 有权
    用于串行闪存测试的时钟倍频器方法和装置

    公开(公告)号：US20080080276A1

    公开(公告)日：2008-04-03

    申请号：US11526124

    申请日：2006-09-22

    申请人： Tien-Ler Lin ,  Kwangho Kim ,  Hui Chen ,  Eungjoon Park

    发明人： Tien-Ler Lin ,  Kwangho Kim ,  Hui Chen ,  Eungjoon Park

    IPC分类号： G11C16/06 ,  G11C29/00 ,  G11C7/00 ,  G11C11/34

    CPC分类号： G11C29/14 ,  G11C7/22 ,  G11C7/222 ,  G11C29/12015

    摘要： Method and apparatus for memory device testing at a higher clock rate than the clock rate provided by a memory tester. The method includes providing a memory tester capable of generating a first clock signal characterized by a first clock frequency, and applying the first clock signal to the memory device. The method also includes receiving a command for activating a high-clock-frequency test mode. The method generates a second clock signal in the memory device in response to the first clock signal. The second clock signal is characterized by a second clock frequency which is higher than the first clock frequency. The method then tests the memory device at the second clock frequency. In a specific embodiment, the method is applied to a serial flash memory device. The invention can also be applied to testing and operating other memory devices or systems that include synchronized circuits.

    摘要翻译： 用于以比由存储器测试器提供的时钟速率更高的时钟速率测试存储器件的方法和装置。 该方法包括提供能够产生以第一时钟频率为特征的第一时钟信号并将第一时钟信号施加到存储器件的存储器测试器。 该方法还包括接收用于激活高时钟频率测试模式的命令。 该方法响应于第一时钟信号在存储器件中产生第二时钟信号。 第二时钟信号的特征在于高于第一时钟频率的第二时钟频率。 然后该方法以第二个时钟频率测试存储器件。 在具体实施例中，该方法被应用于串行闪存设备。 本发明还可以应用于测试和操作包括同步电路的其它存储器件或系统。

    Clock frequency doubler method and apparatus for serial flash testing
    2.
    发明授权
    Clock frequency doubler method and apparatus for serial flash testing 有权
    用于串行闪存测试的时钟倍频器方法和装置

    公开(公告)号：US07502267B2

    公开(公告)日：2009-03-10

    申请号：US11526124

    申请日：2006-09-22

    申请人： Tien-Ler Lin ,  Kwangho Kim ,  Hui Chen ,  Eungjoon Park

    发明人： Tien-Ler Lin ,  Kwangho Kim ,  Hui Chen ,  Eungjoon Park

    IPC分类号： G11C7/00 ,  G11C11/34 ,  G11C8/00

    CPC分类号： G11C29/14 ,  G11C7/22 ,  G11C7/222 ,  G11C29/12015

    摘要： Method and apparatus for memory device testing at a higher clock rate than the clock rate provided by a memory tester. The method includes providing a memory tester capable of generating a first clock signal characterized by a first clock frequency, and applying the first clock signal to the memory device. The method also includes receiving a command for activating a high-clock-frequency test mode. The method generates a second clock signal in the memory device in response to the first clock signal. The second clock signal is characterized by a second clock frequency which is higher than the first clock frequency. The method then tests the memory device at the second clock frequency. In a specific embodiment, the method is applied to a serial flash memory device. The invention can also be applied to testing and operating other memory devices or systems that include synchronized circuits.

    摘要翻译： 用于以比由存储器测试器提供的时钟速率更高的时钟速率测试存储器件的方法和装置。 该方法包括提供能够产生以第一时钟频率为特征的第一时钟信号并将第一时钟信号施加到存储器件的存储器测试器。 该方法还包括接收用于激活高时钟频率测试模式的命令。 该方法响应于第一时钟信号在存储器件中产生第二时钟信号。 第二时钟信号的特征在于高于第一时钟频率的第二时钟频率。 然后该方法以第二个时钟频率测试存储器件。 在具体实施例中，该方法被应用于串行闪存设备。 本发明还可以应用于测试和操作包括同步电路的其它存储器件或系统。

    Nonvolatile memory and method of operation thereof to control erase disturb
    3.
    发明授权
    Nonvolatile memory and method of operation thereof to control erase disturb 有权
    非易失性存储器及其操作方法来控制擦除干扰

    公开(公告)号：US06768671B1

    公开(公告)日：2004-07-27

    申请号：US10382719

    申请日：2003-03-05

    申请人： Poongyeub Lee ,  Joo Weon Park ,  Kwangho Kim ,  Eungjoon Park

    发明人： Poongyeub Lee ,  Joo Weon Park ,  Kwangho Kim ,  Eungjoon Park

    IPC分类号： G11C1616

    CPC分类号： G11C16/08 ,  G11C16/12 ,  G11C16/3418

    摘要： In an array of nonvolatile memory cells, as many memory cells as desired and indeed even the entire array of memory cells may be placed in a single region of the bulk, illustratively a p-well. Peripheral circuitry is used to in effect section the memory array into blocks and groups of blocks, and to establish suitable biasing and counter-biasing within those blocks and groups during page or block erase operations to limit erase disturb. Each group is provided with its own set of voltage switches, which furnishes the bias voltages for the various modes of operation, including erase. Each of the voltage switches furnish either a large positive voltage when its group is selected, or a large negative voltage when its group is unselected. The size of the group is established as a compromise between degree of erase disturb and substrate area required for the voltage switches.

    摘要翻译： 在非易失性存储器单元的阵列中，根据需要，甚至整个存储单元阵列可以将多个存储器单元放置在大块的单个区域中，示例性地为p阱。 外设电路用于将存储器阵列有效地划分为块和块组，并且在页或块擦除操作期间在这些块和组内建立合适的偏置和反偏置以限制擦除干扰。 每个组都有自己的一组电压开关，它们为各种工作模式（包括擦除）提供偏置电压。 每个电压开关在选择组时提供大的正电压，或者当其组被选择时提供大的负电压。 该组的尺寸被确定为电压开关所需的擦除干扰程度和衬底面积之间的折衷。

    Semiconductor device and body bias method thereof
    4.
    发明授权
    Semiconductor device and body bias method thereof 有权
    半导体器件及其体偏置方法

    公开(公告)号：US08988135B2

    公开(公告)日：2015-03-24

    申请号：US14092318

    申请日：2013-11-27

    申请人： Kwangho Kim ,  JinHyuk Jeung ,  HyungJong Ko ,  HoSung Roh ,  Hojin Park ,  Sun-kyu Lee

    发明人： Kwangho Kim ,  JinHyuk Jeung ,  HyungJong Ko ,  HoSung Roh ,  Hojin Park ,  Sun-kyu Lee

    IPC分类号： H01L35/00 ,  G05F3/02 ,  G05F3/20

    CPC分类号： G05F3/02 ,  G05F3/205

    摘要： Exemplary embodiments disclose a semiconductor device which includes a function block including a plurality of transistors; a temperature detector configured to detect a driving temperature of the function block in real time; and an adaptive body bias generator configured to provide a body bias voltage to adaptively adjust leakage currents of the transistors according to the detected driving temperature, wherein the adaptive body bias generator is further configured to generate a body bias voltage corresponding to a predetermined minimum leakage current according to the driving temperature.

    摘要翻译： 示例性实施例公开了一种半导体器件，其包括具有多个晶体管的功能块; 温度检测器，被配置为实时检测功能块的驱动温度; 以及自适应体偏置发生器，其被配置为提供身体偏置电压，以根据检测到的驱动温度自适应地调整晶体管的泄漏电流，其中所述自适应体偏置发生器还被配置为产生对应于预定的最小泄漏电流的体偏置电压 根据驾驶温度。