公开(公告)号：US07913136B2

公开(公告)日：2011-03-22

申请号：US12052844

申请日：2008-03-21

申请人： Tilman Gloekler ,  Michael Kugel ,  Thuyen Le ,  Matthias Woehrle

发明人： Tilman Gloekler ,  Michael Kugel ,  Thuyen Le ,  Matthias Woehrle

IPC分类号： G01R31/28

CPC分类号： G01R31/31716 ,  G01R31/31855

摘要： The present invention relates to a method for performing a logic built-in self-test (LBIST) on an electronic circuit with a plurality of logic circuits (18, 20, 22, 24) and storage elements (14, 16) connected serially to a number of LBIST stumps (10, 12) between a pseudo-random-pattern generator (26) and a multiple-input-signature register (28), wherein at least one constrained logic circuit (18) requires constrained values as input signals. Said method comprises the following steps: scanning the LBIST stumps (10, 12) with the pseudo-random-pattern generator (26), deactivating the multiple-input-signature register (28), performing a functional update in order to propagate legal values into those storage elements (16), which require constrained values, activating or resetting (51) the multiple-input-signature register (28), and setting or programming a start value in a counter (42) for activating a loop back circuit (34) in order to avoid an overwriting of the well-constrained values in the storage elements (16).

摘要翻译： 本发明涉及一种用于在电子电路上执行逻辑内置自检（LBIST）的方法，该电子电路具有多个逻辑电路（18,20,22,24）和串行连接到 伪随机模式生成器（26）和多输入签名寄存器（28）之间的多个LBIST树桩（10,12），其中至少一个约束逻辑电路（18）需要约束值作为输入信号。 所述方法包括以下步骤：用伪随机模式生成器（26）扫描LBIST树桩（10,12），去激活多输入签名寄存器（28），执行功能更新以便传播合法值 进入需要约束值的那些存储元件（16），激活或复位（51）多输入签名寄存器（28），以及在用于激活环回电路的计数器（42）中设置或编程起始值（ 34），以避免在存储元件（16）中覆盖良好约束的值。

公开(公告)号：US20080250289A1

公开(公告)日：2008-10-09

申请号：US12052844

申请日：2008-03-21

申请人： Tilman Gloekler ,  Michael Kugel ,  Thuyen Le ,  Matthias Woehrle

发明人： Tilman Gloekler ,  Michael Kugel ,  Thuyen Le ,  Matthias Woehrle

IPC分类号： G01R31/28

CPC分类号： G01R31/31716 ,  G01R31/31855

摘要： The present invention relates to a method for performing a logic built-in self-test (LBIST) on an electronic circuit with a plurality of logic circuits (18, 20, 22, 24) and storage elements (14, 16) connected serially to a number of LBIST stumps (10, 12) between a pseudo-random-pattern generator (26) and a multiple-input-signature register (28), wherein at least one constrained logic circuit (18) requires constrained values as input signals. Said method comprises the following steps: scanning the LBIST stumps (10, 12) with the pseudo-random-pattern generator (26), deactivating the multiple-input-signature register (28), performing a functional update in order to propagate legal values into those storage elements (16), which require constrained values, activating or resetting (51) the multiple-input-signature register (28), and setting or programming a start value in a counter (42) for activating a loop back circuit (34) in order to avoid an overwriting of the well-constrained values in the storage elements (16).

摘要翻译： 本发明涉及一种用于在电子电路上执行逻辑内置自检（LBIST）的方法，该电子电路具有多个逻辑电路（18,20,22,24）和串行连接到 伪随机模式生成器（26）和多输入签名寄存器（28）之间的多个LBIST树桩（10,12），其中至少一个约束逻辑电路（18）需要约束值作为输入信号。 所述方法包括以下步骤：用伪随机模式生成器（26）扫描LBIST树桩（10,12），去激活多输入签名寄存器（28），执行功能更新以便传播合法值 进入需要约束值的那些存储元件（16），激活或复位（51）多输入签名寄存器（28），以及在用于激活环回电路的计数器（42）中设置或编程起始值（ 34），以避免在存储元件（16）中覆盖良好约束的值。

公开(公告)号：US20080209245A1

公开(公告)日：2008-08-28

申请号：US12029636

申请日：2008-02-12

申请人： Daniel Becker ,  Rafael Keggenhoff ,  Thuyen Le ,  Tobias Webel ,  Matthias Woehrle

发明人： Daniel Becker ,  Rafael Keggenhoff ,  Thuyen Le ,  Tobias Webel ,  Matthias Woehrle

IPC分类号： G06F1/06 ,  G06F1/32

CPC分类号： G06F11/3058 ,  G06F11/3024 ,  G06F11/3419 ,  G06F11/348

摘要： Techniques for accounting microprocessor resource consumption. The present invention provides an automatic method to timely determine the current microprocessor clock frequency. Information provided by timer facilities of the microprocessor is reused by sampling this information at constant intervals. Such direct derivation of the microprocessor clock frequency is a real-time method that also takes into consideration secondary effects. Examples for such secondary effects include clock frequency variations across chips due to manufacturing variations, any degradation due to performance loss by thermal, or other detrimental effects as well as any voltage changes. In the preferred embodiment of the invention, the real-time microprocessor clock frequency determination is implemented as part of the microprocessor itself. No additional service processors or other external hardware facilities are needed in order to control the microprocessor clock frequency determination function.

摘要翻译： 用于会计微处理器资源消耗的技术。 本发明提供了一种能够及时确定当前微处理器时钟频率的自动方法。 由微处理器的定时器设备提供的信息通过以恒定的间隔对该信息进行采样来重用。 微处理器时钟频率的这种直接推导是一种也考虑到二次效应的实时方法。 这种二次效应的示例包括由于制造变化导致的芯片之间的时钟频率变化，由于热损耗导致的任何劣化或其他有害影响以及任何电压变化。 在本发明的优选实施例中，实时微处理器时钟频率确定被实现为微处理器本身的一部分。 为了控制微处理器的时钟频率确定功能，不需要附加的服务处理器或其他外部硬件设备。

公开(公告)号：US08140885B2

公开(公告)日：2012-03-20

申请号：US12029636

申请日：2008-02-12

申请人： Daniel Becker ,  Rafael Keggenhoff ,  Thuyen Le ,  Tobias Webel ,  Matthias Woehrle

发明人： Daniel Becker ,  Rafael Keggenhoff ,  Thuyen Le ,  Tobias Webel ,  Matthias Woehrle

IPC分类号： G06F1/08

CPC分类号： G06F11/3058 ,  G06F11/3024 ,  G06F11/3419 ,  G06F11/348

摘要： Techniques for accounting microprocessor resource consumption. The present invention provides an automatic method to timely determine the current microprocessor clock frequency. Information provided by timer facilities of the microprocessor is reused by sampling this information at constant intervals. Such direct derivation of the microprocessor clock frequency is a real-time method that also takes into consideration secondary effects. Examples for such secondary effects include clock frequency variations across chips due to manufacturing variations, any degradation due to performance loss by thermal, or other detrimental effects as well as any voltage changes. In the preferred embodiment of the invention, the real-time microprocessor clock frequency determination is implemented as part of the microprocessor itself. No additional service processors or other external hardware facilities are needed in order to control the microprocessor clock frequency determination function.

摘要翻译： 用于会计微处理器资源消耗的技术。 本发明提供了一种能够及时确定当前微处理器时钟频率的自动方法。 由微处理器的定时器设备提供的信息通过以恒定的间隔对该信息进行采样来重用。 微处理器时钟频率的这种直接推导是一种也考虑到二次效应的实时方法。 这种二次效应的示例包括由于制造变化导致的芯片之间的时钟频率变化，由于热损耗导致的任何劣化或其他有害影响以及任何电压变化。 在本发明的优选实施例中，实时微处理器时钟频率确定被实现为微处理器本身的一部分。 为了控制微处理器的时钟频率确定功能，不需要附加的服务处理器或其他外部硬件设备。

公开(公告)号：US20080222400A1

公开(公告)日：2008-09-11

申请号：US12043168

申请日：2008-03-06

申请人： Daniel Becker ,  Cedric Lichtenau ,  Thomas Pflunger ,  Matthias Woehrle

发明人： Daniel Becker ,  Cedric Lichtenau ,  Thomas Pflunger ,  Matthias Woehrle

IPC分类号： G06F9/312

CPC分类号： G06F9/3842 ,  G06F11/3466 ,  G06F2201/86 ,  G06F2201/88 ,  Y02D10/34

摘要： Reduction of power consumption and chip area of a microprocessor employing speculative performance counting, comprising splitting a counter and a backup register of a speculative counting mechanism performing the speculative performance counting into first and second parts each, re-using an available storage within the microprocessor as first parts respectively; integrating at least one dedicated pre-counter into the microprocessor as second parts respectively; splitting the data handled by the speculative counting mechanism in high-order and low-order bits; storing the high order bits in the first parts; storing the low order bits in the second parts; updating the first parts periodically; and saving and propagating the carry-out from the second parts to high-order bits when a corresponding first part of the second parts is next updated respectively.

摘要翻译： 减少使用推测性能计数的微处理器的功耗和芯片面积，包括将执行推测性能计数的推测性计数机制的计数器和备用寄存器分别分成第一和第二部分，重新​​使用微处理器内的可用存储器 第一部分; 将至少一个专用预计数器分别作为第二部分集成到微处理器中; 将由推测计数机制处理的数据分解成高阶和低位; 将高位位存储在第一部分中; 将低位位存储在第二部分中; 定期更新第一部分; 并且分别在下一次更新对应的第二部分的第一部分时，将进位从第二部分保存并传播到高位。

公开(公告)号：US20080215906A1

公开(公告)日：2008-09-04

申请号：US12116652

申请日：2008-05-07

申请人： Scott Barnett Swaney ,  Kenneth Lundy Ward ,  Tobias Webel ,  Ulrich Weiss ,  Matthias Woehrle

发明人： Scott Barnett Swaney ,  Kenneth Lundy Ward ,  Tobias Webel ,  Ulrich Weiss ,  Matthias Woehrle

IPC分类号： G06F1/12

CPC分类号： G06F11/1604 ,  G06F1/14 ,  G06F11/20

摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.

摘要翻译： 冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。 步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。 独立的步进同步信号被传送到几个同级芯片。 本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。 可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。 主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。 所有剩余的芯片都是从芯片。 拓扑的所有段都是冗余的。 多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。 命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。

公开(公告)号：US07865758B2

公开(公告)日：2011-01-04

申请号：US12140028

申请日：2008-06-16

申请人： Scott Barnett Swaney ,  Kenneth Lundy Ward ,  Tobias Webel ,  Ulrich Weiss ,  Matthias Woehrle

发明人： Scott Barnett Swaney ,  Kenneth Lundy Ward ,  Tobias Webel ,  Ulrich Weiss ,  Matthias Woehrle

IPC分类号： G06F1/12

CPC分类号： G06F11/1604 ,  G06F1/14 ,  G06F11/20

摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.

摘要翻译： 冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。 步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。 独立的步进同步信号被传送到几个同级芯片。 本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。 可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。 主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。 所有剩余的芯片都是从芯片。 拓扑的所有段都是冗余的。 多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。 命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。

公开(公告)号：US20080244300A1

公开(公告)日：2008-10-02

申请号：US12140028

申请日：2008-06-16

申请人： Scott Barnett Swaney ,  Kenneth Lundy Ward ,  Tobias Webel ,  Ulrich Weiss ,  Matthias Woehrle

发明人： Scott Barnett Swaney ,  Kenneth Lundy Ward ,  Tobias Webel ,  Ulrich Weiss ,  Matthias Woehrle

IPC分类号： G06F1/12

CPC分类号： G06F11/1604 ,  G06F1/14 ,  G06F11/20

摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.

摘要翻译： 冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。 步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。 独立的步进同步信号被传送到几个同级芯片。 本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。 可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。 主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。 所有剩余的芯片都是从芯片。 拓扑的所有段都是冗余的。 多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。 命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。

公开(公告)号：US07761726B2

公开(公告)日：2010-07-20

申请号：US12116652

申请日：2008-05-07

申请人： Scott Barnett Swaney ,  Kenneth Lundy Ward ,  Tobias Webel ,  Ulrich Weiss ,  Matthias Woehrle

发明人： Scott Barnett Swaney ,  Kenneth Lundy Ward ,  Tobias Webel ,  Ulrich Weiss ,  Matthias Woehrle

IPC分类号： G06F1/12

CPC分类号： G06F11/1604 ,  G06F1/14 ,  G06F11/20

摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.

摘要翻译： 冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。 步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。 独立的步进同步信号被传送到几个同级芯片。 本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。 可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。 主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。 所有剩余的芯片都是从芯片。 拓扑的所有段都是冗余的。 多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。 命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。

公开(公告)号：US07487377B2

公开(公告)日：2009-02-03

申请号：US11054294

申请日：2005-02-09

申请人： Scott Barnett Swaney ,  Kenneth Lundy Ward ,  Tobias Webel ,  Ulrich Weiss ,  Matthias Woehrle

发明人： Scott Barnett Swaney ,  Kenneth Lundy Ward ,  Tobias Webel ,  Ulrich Weiss ,  Matthias Woehrle

IPC分类号： G06F13/42

CPC分类号： G06F11/1604 ,  G06F1/14 ,  G06F11/20

摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.

摘要翻译： 冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。 步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。 独立的步进同步信号被传送到几个同级芯片。 本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。 可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。 主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。 所有剩余的芯片都是从芯片。 拓扑的所有段都是冗余的。 多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。 命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。