公开(公告)号：US6010938A

公开(公告)日：2000-01-04

申请号：US192018

申请日：1998-11-11

Applicant: Ting-Sing Wang ,  Chon-Shin Jou ,  Kuan-Chou Sung

Inventor： Ting-Sing Wang ,  Chon-Shin Jou ,  Kuan-Chou Sung

IPC: H01L21/00

CPC classification number: H01L28/20 ,  H01L27/1112

Abstract: The present invention provides a new method for making a load resistor in a semiconductor chip. According to the new method, a linear-shaped doped polysilicon layer is formed onto the surface of the semiconductor chip that comprises a Si substrate and an NSG layer. This layer functions as a conductive path. A slot is formed in this layer by removing a section from the conductive path. This slot reaches down to the NSG layer effectively cutting off the polysilicon layer. Then, a rugged polysilicon layer is evenly deposited onto the surface of the slot for connection of the conductive path. The polysilicon layer over the slot and the doped polysilicon layer defines the load resistor. The result is a high resistance value with usage of only a small space.

Abstract translation: 本发明提供一种在半导体芯片中制造负载电阻的新方法。 根据新方法，在包括Si衬底和NSG层的半导体芯片的表面上形成线状掺杂多晶硅层。 该层用作导电路径。 通过从导电路径去除一部分，在该层中形成槽。 该槽向下到达NSG层，有效地切断了多晶硅层。 然后，将坚固的多晶硅层均匀地沉积到槽的表面上以连接导电路径。 槽上的多晶硅层和掺杂多晶硅层限定了负载电阻。 结果是具有仅较小空间的高电阻值。

公开(公告)号：US07319058B2

公开(公告)日：2008-01-15

申请号：US11161724

申请日：2005-08-15

Applicant: Ting-Sing Wang

Inventor： Ting-Sing Wang

IPC: H01L21/336

CPC classification number: H01L29/7923 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7926

Abstract: A fabrication method for a non-volatile memory is provided. To fabricate the non-volatile memory, a plurality of first trenches and second trenches are formed in a substrate, wherein the second trenches are disposed above the first trenches and cross over the first trenches. Then, a tunneling layer and a charge storage layer are sequentially formed on both sidewalls of each second trench. An isolation layer is filled into the first trench. Furthermore, a charge barrier layer is formed on the sidewall of the second trench, and a gate dielectric layer is formed at the bottom of the second trench. A control gate layer is filled into the second trench. Finally, two first doping regions are formed in the substrate at both sides of the control gate layer.

Abstract translation: 提供了一种用于非易失性存储器的制造方法。 为了制造非易失性存储器，在衬底中形成多个第一沟槽和第二沟槽，其中第二沟槽设置在第一沟槽上方并跨过第一沟槽。 然后，在每个第二沟槽的两个侧壁上依次形成隧穿层和电荷存储层。 隔离层被填充到第一沟槽中。 此外，在第二沟槽的侧壁上形成电荷阻挡层，在第二沟槽的底部形成栅极电介质层。 控制栅极层被填充到第二沟槽中。 最后，在控制栅极层两侧的衬底中形成两个第一掺杂区。

公开(公告)号：US4917467A

公开(公告)日：1990-04-17

申请号：US207753

申请日：1988-06-16

Applicant: Hsiung-Ku Chen ,  Ting-Sing Wang ,  Chia-Wei Hao

Inventor： Hsiung-Ku Chen ,  Ting-Sing Wang ,  Chia-Wei Hao

IPC: G02F1/133 ,  G02F1/1343 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/36 ,  H01L21/336 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L49/02

CPC classification number: H01L27/12 ,  G02F1/13624 ,  G02F1/136259

Abstract: A TFT LCD device is comprised of four TFT's with two separate sources, two separate drains and one common source-drain which is shared by the four respective TFT's, either acting as source or drain. The gate structure employs only one gate line with a bypass line. By sharing of the Si island and the centralization of the gate electrode of four TFT's, the pixel open ratio increases quite substantially. The devices are connected to the two adjacent pixels separated by the gate line via the two drain electrodes. Each pixel electrode is connected to the two adjacent devices via the two drain electrodes. Each pixel electrode can receive the data signals which are controlled by the two adjacent devices, to form a redundant structure for improving the yield of the TFT LCD. The common source-drain is situated along the gate bus line, and doesn't occupy too much of the pixel area, to thereby provide a large open ratio.

Abstract translation: TFT LCD器件由四个TFT组成，具有两个独立的源极，两个独立的漏极和一个共同的源极 - 漏极，由四个相应的TFT共享，作为源极或漏极。 栅极结构仅使用一条带旁路线的栅极线。 通过共享Si岛和四个TFT的栅电极的集中，像素开放比率显着增加。 这些器件通过两个漏电极连接到由栅极线分开的两个相邻像素。 每个像素电极经由两个漏电极连接到两个相邻的器件。 每个像素电极可以接收由两个相邻器件控制的数据信号，以形成用于提高TFT LCD的产量的冗余结构。 公共源极 - 漏极沿着栅极总线布置，并且不占用像素面积太多，从而提供大的开放比。

公开(公告)号：US20070120151A1

公开(公告)日：2007-05-31

申请号：US11668477

申请日：2007-01-30

Applicant: Ting-Sing Wang

Inventor： Ting-Sing Wang

IPC: H01L29/76

CPC classification number: H01L29/7923 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7926

Abstract: A NVM including a substrate, a control gate layer, a charge storage layer, a tunneling layer, a charge barrier layer, a gate dielectric layer and a first doping region is described. The control gate layer is disposed in a first trench of the substrate; the charge storage layer is disposed between the sidewall of the first trench and the control gate layer; the tunneling layer is disposed between the sidewall of the first trench and the charge storage layer; the charge barrier layer is disposed between the charge storage layer and the control gate layer; the gate dielectric layer is disposed between the bottom of the first trench and the control gate layer; and the first doping region is disposed in the substrate at one side of the control gate layer.

Abstract translation: 描述了包括基板，控制栅极层，电荷存储层，隧道层，电荷势垒层，栅极介电层和第一掺杂区域的NVM。 控制栅极层设置在衬底的第一沟槽中; 电荷存储层设置在第一沟槽的侧壁和控制栅极层之间; 隧道层设置在第一沟槽的侧壁和电荷存储层之间; 电荷阻挡层设置在电荷存储层和控制栅极层之间; 栅介电层设置在第一沟槽的底部和控制栅极层之间; 并且第一掺杂区域设置在控制栅极层的一侧的衬底中。

公开(公告)号：US20060275976A1

公开(公告)日：2006-12-07

申请号：US11161724

申请日：2005-08-15

Applicant: Ting-Sing Wang

Inventor： Ting-Sing Wang

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/76

CPC classification number: H01L29/7923 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7926

Abstract: A fabrication method for a non-volatile memory is provided. To fabricate the non-volatile memory, a plurality of first trenches and second trenches are formed in a substrate, wherein the second trenches are disposed above the first trenches and cross over the first trenches. Then, a tunneling layer and a charge storage layer are sequentially formed on both sidewalls of each second trench. An isolation layer is filled into the first trench. Furthermore, a charge barrier layer is formed on the sidewall of the second trench, and a gate dielectric layer is formed at the bottom of the second trench. A control gate layer is filled into the second trench. Finally, two first doping regions are formed in the substrate at both sides of the control gate layer.

Abstract translation: 提供了一种用于非易失性存储器的制造方法。 为了制造非易失性存储器，在衬底中形成多个第一沟槽和第二沟槽，其中第二沟槽设置在第一沟槽上方并跨过第一沟槽。 然后，在每个第二沟槽的两个侧壁上依次形成隧穿层和电荷存储层。 隔离层被填充到第一沟槽中。 此外，在第二沟槽的侧壁上形成电荷阻挡层，在第二沟槽的底部形成栅极电介质层。 控制栅极层被填充到第二沟槽中。 最后，在控制栅极层两侧的衬底中形成两个第一掺杂区。

公开(公告)号：US06180980B2

公开(公告)日：2001-01-30

申请号：US09376464

申请日：1999-08-18

Applicant: Ting-Sing Wang

Inventor： Ting-Sing Wang

IPC: H01L2178

CPC classification number: H01L29/66825 ,  H01L21/28273

Abstract: A method of manufacturing a trench non-volatile memory cell, comprises the steps of: providing a semiconductor substrate; performing ion implantation to form a source region in the semiconductor substrate; forming a trench on the semiconductor substrate by silicon etching, the trench reaching down to the source region; growing a first isolation layer on the surface of the semiconductor substrate, and the bottom and sidewall of the trench; forming a hollow-shaped first conducting layer in the trench; performing thermal oxidation on the first conducting layer to form a bird's beak isolation layer and a floating gate, which are the oxidized and unoxidized part of the first conducting layer, respectively, wherein the floating gate has a peak; partially removing the first isolation layer and the bird's beak isolation layer to bare the surface of the semiconductor substrate, the peak and the sidewall of the trench; depositing a second conducting layer; patterning the second conducting layer to form a control gate; and defining a drain region in the semiconductor substrate.

Abstract translation: 一种制造沟槽非易失性存储单元的方法，包括以下步骤：提供半导体衬底; 执行离子注入以在半导体衬底中形成源极区; 通过硅蚀刻在半导体衬底上形成沟槽，沟槽到达源区; 在半导体衬底的表面上以及沟槽的底部和侧壁上生长第一隔离层; 在沟槽中形成中空状的第一导电层; 在所述第一导电层上进行热氧化以形成分别为所述第一导电层的氧化和未氧化部分的鸟喙隔离层和浮栅，其中所述浮栅具有峰; 部分地去除第一隔离层和鸟嘴隔离层以露出半导体衬底的表面，沟槽的峰和侧壁; 沉积第二导电层; 图案化第二导电层以形成控制栅极; 以及限定半导体衬底中的漏区。

公开(公告)号：US20080070371A1

公开(公告)日：2008-03-20

申请号：US11566761

申请日：2006-12-05

Applicant: Ting-Sing Wang

Inventor： Ting-Sing Wang

IPC: H01L21/336

CPC classification number: H01L29/1045 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor device includes a substrate, a gate electrode, a pair of first impurity regions, a pair of second impurity regions and at least one dummy pattern. The gate electrode is positioned above the substrate. The first impurity regions are positioned in the substrate and near both sides of the gate electrode. The second impurity regions are positioned in the first impurity regions respectively, and the dopant concentration of the first impurity regions is lower than the dopant concentration of the second impurity regions. The dummy pattern is positioned over the first impurity regions and exposes the second impurity regions.

Abstract translation: 半导体器件包括衬底，栅极电极，一对第一杂质区域，一对第二杂质区域和至少一个虚拟图案。 栅电极位于衬底上方。 第一杂质区位于基板中并靠近栅电极的两侧。 第二杂质区域分别位于第一杂质区域中，第一杂质区域的掺杂剂浓度低于第二杂质区域的掺杂剂浓度。 虚设图案位于第一杂质区上方并暴露第二杂质区。

公开(公告)号：US06774394B2

公开(公告)日：2004-08-10

申请号：US10061562

申请日：2002-02-01

Applicant: Ting-Sing Wang

Inventor： Ting-Sing Wang

IPC: H01L2358

CPC classification number: H01L21/76897 ,  H01L22/34

Abstract: The present invention provides an inline detection device for self-aligned contact defects, formed in a semiconductor substrate, comprising: an active area, formed in the semiconductor substrate, comprised of a serpentine gate having spacers on the side, a plurality of first contact windows nested immediately between the same spacers, a plurality of first contact plugs formed in the first contact windows, and two probing pads, formed in the semiconductor substrate, comprised of a plurality of matrix gates, a second contact window exposing portions of the matrix gates, and a second contact plug formed in the second contact window.

Abstract translation: 本发明提供了一种形成在半导体衬底中的自对准接触缺陷的在线检测装置，包括：形成在半导体衬底中的有源区，包括在侧面具有间隔物的蛇形栅极，多个第一接触窗口 立即嵌套在相同间隔件之间，形成在第一接触窗中的多个第一接触插塞和形成在半导体衬底中的两个探测焊盘，包括多个矩阵栅极，暴露矩阵栅极部分的第二接触窗口， 以及形成在第二接触窗口中的第二接触插塞。

公开(公告)号：US06677608B2

公开(公告)日：2004-01-13

申请号：US10004755

申请日：2001-12-03

Applicant: Ting-Sing Wang

Inventor： Ting-Sing Wang

IPC: H01L2912

CPC classification number: H01L22/34

Abstract: The present invention provides a semiconductor device for detecting gate defects and the method of using the same to detect gate defects. The semiconductor device is comprised of a semiconductor substrate having an oxide layer on the top, a gate having spacers, formed on the oxide layer and surrounding the semiconductor substrate, wherein the gate is also patterned to divide the semiconductor substrate into two parts not electrically connected, and a conductive layer formed on the semiconductor outside the gate. In addition, the method for using the semiconductor device of the present invention to detect gate defects is comprised of applying a ground voltage and a set voltage respectively to two parts divided by the gate in the semiconductor device, and measuring current between the two parts.

Abstract translation: 本发明提供一种用于检测栅极缺陷的半导体器件及其使用该方法来检测栅极缺陷。 半导体器件由在顶部具有氧化物层的半导体衬底，形成在氧化物层上并包围半导体衬底的间隔物的栅极组成，其中栅极也被图案化以将半导体衬底分成两个部分而不是电连接 以及形成在栅极外部的半导体上的导电层。 此外，使用本发明的半导体器件来检测栅极缺陷的方法包括分别将接地电压和设定电压施加到由半导体器件中的栅极划分的两个部分以及测量两个部分之间的电流。

公开(公告)号：US5824234A

公开(公告)日：1998-10-20

申请号：US725122

申请日：1996-10-02

Applicant: Chon-Shin Jou ,  Ting-Sing Wang ,  Chun-Lin Chen ,  Ming-Huan Tsai ,  Ming-Ru Tsai

Inventor： Chon-Shin Jou ,  Ting-Sing Wang ,  Chun-Lin Chen ,  Ming-Huan Tsai ,  Ming-Ru Tsai

IPC: H01L21/311 ,  H01L21/60 ,  H01L21/00

CPC classification number: H01L21/31138 ,  H01L24/03 ,  H01L2224/0381 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029

Abstract: The present invention provides a method for forming a bonding pad having a low contact resistance. The method includes steps of: a) forming a bonding pad structure on a substrate having a metal layer by forming a passivation layer over said metal layer and etching the passivation layer with a fluorine-containing gas by which a fluorine-containing layer is formed on a surface of said bonding pad structure; and b) removing the fluorine-containing layer for reducing a contact resistance of said bonding pad structure.

Abstract translation: 本发明提供一种形成接触电阻低的焊盘的方法。 该方法包括以下步骤：a）在具有金属层的衬底上形成焊盘结构，在所述金属层上形成钝化层，并用形成含氟层的含氟气体蚀刻钝化层 所述焊盘结构的表面; 以及b）除去所述含氟层以降低所述接合焊盘结构的接触电阻。