公开(公告)号：US06794058B2

公开(公告)日：2004-09-21

申请号：US10350110

申请日：2003-01-24

Applicant: Tsuyoshi Honda ,  Tatsuya Kanamaru ,  Eiichi Asano ,  Toshio Shiobara

Inventor： Tsuyoshi Honda ,  Tatsuya Kanamaru ,  Eiichi Asano ,  Toshio Shiobara

IPC: H01L2912

CPC classification number: C08K3/22 ,  C08K3/36 ,  C08K2003/2237 ,  Y10T428/12528 ,  C08L63/00

Abstract: A flip-chip type semiconductor device sealed with a light transmissive epoxy resin composition comprising (A) an epoxy resin having the following general formula (i):  wherein n is 0 or a positive number, (B) a curing accelerator, and (C) an amorphous silica-titania co-melt as at least one of inorganic fillers, said composition satisfying the relationship of the following formula (1): [ { 2 ⁢ ( n A 2 + n C 2 ) - ( n A + n C ) 2 } / 2 ] 1 / 2

Abstract translation: 一种用透光性环氧树脂组合物密封的倒装芯片型半导体器件，其包含（A）具有以下通式（i）的环氧树脂：其中n为0或正数，（B）固化促进剂和（C ）无定形二氧化硅 - 二氧化钛共熔体作为无机填料中的至少一种，所述组合物满足下式（1）的关系：其中nA是组合物的固化产物在25℃以下的折射率，不包括 无机填料，nC是25℃下的无机填料的折射率。

公开(公告)号：US06734527B1

公开(公告)日：2004-05-11

申请号：US10316826

申请日：2002-12-12

Applicant: Qi Xiang

Inventor： Qi Xiang

IPC: H01L2912

CPC classification number: H01L21/823857 ,  H01L21/823807

Abstract: CMOS devices with balanced drive currents are formed with a PMOS transistor based on SiGe and a deposited high-k gate dielectric. Embodiments including forming a composite substrate comprising a layer of strained Si on a layer of SiGe, forming isolation regions defining a PMOS region and an NMOS region, forming a thermal oxide layer on the strained Si layer, selectively removing the thermal oxide layer and strained Si layer from the PMOS region, depositing a layer of high-k material on the layer of SiGe in the PMOS region and then forming gate electrodes in the PMOS and NMOS regions.

Abstract translation: 具有平衡驱动电流的CMOS器件由基于SiGe的PMOS晶体管和沉积的高k栅极电介质形成。 实施例包括在SiGe层上形成包括应变硅层的复合衬底，形成限定PMOS区域的隔离区域和在应变Si层上形成热氧化物层的NMOS区域，选择性地去除热氧化物层和应变Si 层，在PMOS区域中的SiGe层上沉积高k材料层，然后在PMOS和NMOS区域中形成栅电极。

公开(公告)号：US06733901B2

公开(公告)日：2004-05-11

申请号：US10136484

申请日：2002-05-02

Applicant: Noriyuki Takasaki ,  Kenji Takayama ,  Kazuo Noda

Inventor： Noriyuki Takasaki ,  Kenji Takayama ,  Kazuo Noda

IPC: H01L2912

CPC classification number: H01L23/293 ,  C08G59/18 ,  C08L61/06 ,  C08L63/00 ,  C08L65/00 ,  H01L2924/0002 ,  Y10T428/12528 ,  Y10T428/31511 ,  C08L2666/22 ,  C08L2666/16 ,  H01L2924/00

Abstract: The present invention provides a process for producing an epoxy resin composition for semiconductor encapsulation which, when used in encapsulation of a semiconductor chip, can minimize voids appearing in the semiconductor device obtained. That is, the present invention provides a process for producing an epoxy resin composition for semiconductor encapsulation, which comprises premixing raw materials containing at least an epoxy resin, a phenolic resin, a curing accelerator and an inorganic filler, then grinding the resulting premix using a grinder to obtain a ground material having such a particle size distribution that particles having particle diameters of 250 &mgr;m or more are 10% by weight or less, particles having particle diameters of 150 &mgr;m to less than 250 &mgr;m are 15% by weight or less and particles having particle diameters of less than 150 &mgr;m are 75% by weight or more, and melt-kneading the ground material under a reduced pressure, or melt-kneading the ground material and then exposing the resulting molten material to a reduced pressure.

Abstract translation: 本发明提供一种半导体封装用环氧树脂组合物的制造方法，其在半导体芯片的封装中使用时，能够最小化所获得的半导体装置中的空隙。 也就是说，本发明提供一种半导体封装用环氧树脂组合物的制造方法，其特征在于，含有至少包含环氧树脂，酚醛树脂，固化促进剂和无机填料的原料预混合，然后使用 研磨机得到具有粒径为250μm以上的粒子为10重量％以下的粒径分布的研磨材料，粒径为150μm以上且小于250μm的粒子为15重量％以下， 粒径小于150μm的粒子为75重量％以上，在减压下熔融捏合研磨材料，或熔融捏合研磨材料，然后使得到的熔融材料暴露于减压状态。

公开(公告)号：US06707061B2

公开(公告)日：2004-03-16

申请号：US10048478

申请日：2002-07-22

Applicant: Takuya Komoda ,  Yoshiaki Honda ,  Koichi Aizawa ,  Tsutomu Ichihara ,  Yoshifumi Watabe ,  Takashi Hatai ,  Toru Baba

Inventor： Takuya Komoda ,  Yoshiaki Honda ,  Koichi Aizawa ,  Tsutomu Ichihara ,  Yoshifumi Watabe ,  Takashi Hatai ,  Toru Baba

IPC: H01L2912

CPC classification number: B82Y10/00 ,  H01J1/312 ,  H01J2329/00

Abstract: In a field emission-type electron source (10), lower electrodes (8) made of an electroconductive layer, a strong field drift layer (6) including drift portions (6a) made of an oxidized or nitrided porous semiconductor, and surface electrodes (7) made of a metal layer are provided on an upper side of a dielectric substrate (11) made of glass. When voltage is applied to cause the surface electrodes (7) to be anodic with respect to the lower electrodes (8), electrons injected from the lower electrodes (8) to the strong field drift layer (6) are led to drift through the strong field drift layer (6) and are emitted outside through the surface electrodes (7). A pn-junction semiconductor layer composed of an n-layer (21) and a p-layer (22) is provided between the lower electrode (8) and the strong field drift layer (6) to prevent a leakage current from flowing to the surface electrode (7) from the lower electrode (8), thereby reducing amount of power consumption.

Abstract translation: 在场致发射型电子源（10）中，由导电层制成的下电极（8）包括由氧化或氮化多孔半导体制成的漂移部分（6a）的强场漂移层（6）和表面电极 7）由金属层制成，设置在由玻璃制成的电介质基板（11）的上侧。 当施加电压以使表面电极（7）相对于下电极（8）呈阳极时，从下电极（8）注入的强电场漂移层（6）的电子通过强电场 场漂移层（6），并通过表面电极（7）发射到外部。 在下电极（8）和强场漂移层（6）之间设置由n层（21）和p层（22）构成的pn结半导体层，以防止漏电流流向 表面电极（7），从而减少功耗。

公开(公告)号：US06521354B1

公开(公告)日：2003-02-18

申请号：US09806733

申请日：2001-04-04

Applicant: Hiroo Shimizu ,  Katsuhiro Niwa ,  Masayuki Tanaka

Inventor： Hiroo Shimizu ,  Katsuhiro Niwa ,  Masayuki Tanaka

IPC: H01L2912

CPC classification number: C08L63/00 ,  C08K3/36 ,  H01L23/293 ,  H01L2924/0002 ,  Y10T428/12528 ,  H01L2924/00

Abstract: An epoxy resin comprising (A) an epoxy resin, (B) a curing agent and (C) a filler, in which the epoxy resin (A) contains a bisphenol F-type epoxy compound (a), the filler (C) contains spherical silica and the filler (C) accounts for from 88 to 96% by weight of the resin composition, has good soldering heat resistance enough for high-temperature solder reflow and has good moldability. A semiconductor device encapsulated with the resin composition is useful for use in electronic appliances.

Abstract translation: 环氧树脂包含（A）环氧树脂，（B）固化剂和（C）填料，其中环氧树脂（A）含有双酚F型环氧化合物（a），填料（C）含 球形二氧化硅和填料（C）占树脂组合物的88〜96重量％，对于高温回流焊具有良好的焊接耐热性，并且具有良好的成型性。 用树脂组合物封装的半导体器件可用于电子设备。

公开(公告)号：US06507105B1

公开(公告)日：2003-01-14

申请号：US09498338

申请日：2000-02-04

Applicant: Shin-ichi Yamagata ,  Osamu Suwata ,  Chihiro Kawai ,  Akira Fukui ,  Yoshinobu Takeda

Inventor： Shin-ichi Yamagata ,  Osamu Suwata ,  Chihiro Kawai ,  Akira Fukui ,  Yoshinobu Takeda

IPC: H01L2912

CPC classification number: H01L23/142 ,  C22C29/065 ,  C22C32/0063 ,  H01L23/15 ,  H01L23/3733 ,  H01L2924/0002 ,  H05K1/05 ,  H01L2924/00

Abstract: A member for semiconductor devices comprising a composite alloy of aluminum or an aluminum alloy and silicon carbide, wherein silicon carbide grains are dispersed in aluminum or the aluminum alloy in an amount of from 10 to 70% by weight, the amount of nitrogen in the surface of the member is larger than that in the inside thereof, and the ratio of aluminum or the aluminum alloy to silicon carbide is the same in the surface and the inside. The member is produced by mixing powdery materials of aluminum or an aluminum alloy and silicon carbide, compacting the mixed powder, and sintering the compact in a non-oxidizing atmosphere containing nitrogen gas, at a temperature between 600° C. and the melting point of aluminum. The member is lightweight and has high thermal conductivity as well as thermal expansion coefficient which is well matches with that of ceramics and others. Therefore, the member is especially favorable to high-power devices.

Abstract translation: 包括铝或铝合金的复合合金和碳化硅的半导体器件的构件，其中碳化硅颗粒以10至70重量％的量分散在铝或铝合金中，表面中的氮的量 的构件比其内部大，铝或铝合金与碳化硅的比例在表面和内部相同。 该构件通过混合铝或铝合金的粉末材料和碳化硅，压制混合粉末，并在含有氮气的非氧化性气氛中，在600℃的温度和 铝。 该部件重量轻，导热系数高，热膨胀系数高，与陶瓷等相匹配。 因此，该会员特别有利于大功率设备。

公开(公告)号：US06458472B1

公开(公告)日：2002-10-01

申请号：US09755146

申请日：2001-01-08

Applicant: Mark M. Konarski ,  J. Paul Krug

Inventor： Mark M. Konarski ,  J. Paul Krug

IPC: H01L2912

CPC classification number: H01L21/563 ,  B23K35/3612 ,  B23K35/3613 ,  B23K35/3618 ,  H01L23/293 ,  H01L24/29 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01077 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15787 ,  Y10T29/49158 ,  Y10T29/4916 ,  Y10T29/49171 ,  Y10T428/12528 ,  Y10T428/31511 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/0401

Abstract: This invention relates to fluxing underfill compositions useful for fluxing metal surfaces in preparation for providing an electrical connection and sealing the space between semiconductor devices, such as chip size or chip scale packages (“CSPs”), ball grid arrays (“BGAs”), land grid arrays (“LGAs”), flip chip assemblies (“FCs”) and the like, each of which having a semiconductor chip, such as large scale integration (“LSI”), or semiconductor chips themselves and a circuit board to which the devices or chips, respectively, are electrically interconnected. The inventive fluxing underfill composition begins to cure at about the same temperature that solder used to establish the electrical interconnection melts.

Abstract translation: 本发明涉及用于助熔金属表面的助焊剂底部填充组合物，以准备提供电连接并密封半导体器件之间的空间，例如芯片尺寸或芯片尺寸封装（“CSP”），球栅阵列（“BGA”）， 每个都具有半导体芯片，例如大规模集成（“LSI”）或半导体芯片本身的电路阵列（“LGAs”），倒装芯片组件（“FC”）等，以及电路板 设备或芯片分别电连接。 本发明的助焊剂底部填充组合物在与用于建立电互连熔体的焊料大约相同的温度下开始固化。

公开(公告)号：US06417519B1

公开(公告)日：2002-07-09

申请号：US09565486

申请日：2000-05-05

Applicant: Kenji Imanishi ,  Tsuyoshi Takahashi

Inventor： Kenji Imanishi ,  Tsuyoshi Takahashi

IPC: H01L2912

CPC classification number: H01L29/66462 ,  H01L29/201 ,  H01L29/7783

Abstract: A carrier transit layer made of group III-V compound semiconductor is formed on a semiconductor substrate. A carrier supply layer is formed on the carrier transit layer. The carrier supply layer supplies carriers for generating two-dimensional carrier gas in an interface between the carrier supply layer and carrier transit layer. The carrier supply layer is made of group III-V compound semiconductor which contains In as group III element. A gate electrode is disposed above a partial area of the carrier supply layer. An intermediate layer is disposed between the gate electrode and carrier supply layer. The intermediate layer is made of group III-V compound semiconductor not containing In as group III element. An ohmic electrode is disposed on both sides of the gate electrode.

Abstract translation: 在半导体衬底上形成由III-V族化合物半导体制成的载流子迁移层。 载体供给层形成在载体运送层上。 载体供给层在载体供给层和载体运送层之间的界面中提供用于产生二维载气的载体。 载体供给层由含有In作为III族元素的III-V族化合物半导体制成。 栅电极设置在载体供给层的部分区域的上方。 中间层设置在栅电极和载体供给层之间。 中间层由不含In作为III族元素的III-V族化合物半导体制成。 欧姆电极设置在栅电极的两侧。

公开(公告)号：US06319619B1

公开(公告)日：2001-11-20

申请号：US09403311

申请日：1999-10-20

Applicant: Yuko Yamamoto ,  Miho Yamaguchi ,  Hitomi Shigyo

Inventor： Yuko Yamamoto ,  Miho Yamaguchi ,  Hitomi Shigyo

IPC: H01L2912

CPC classification number: H01L23/293 ,  C08K3/22 ,  C08L63/00 ,  H01L2924/0002 ,  Y10T428/12528 ,  Y10T428/31511 ,  Y10T428/31529 ,  C08L61/04 ,  H01L2924/00

Abstract: The present invention relates to a semiconductor encapsulating resin composition which is safe and superior in moisture resistance, flame retardance and moldability, and to a highly reliable semiconductor device which is fabricated by encapsulating a semiconductor element with such a semiconductor encapsulating resin composition. The resin composition according to the present invention comprises a thermosetting resin, a hardening agent and a compound metal hydroxide of polyhedral crystal form represented by the following general formula (1): m(MaOb).n(QdOe).cH2O  (1) [wherein M and Q are different metal elements; Q is a metal element which belongs to a group selected from IVa, Va, VIa, VIIa, VIII, Ib and IIb groups in the periodic table; m, n, a, b, c, d and e, which may be the same or different, each represents a positive number]. In accordance with the present invention, reduction in the fluidity of the resin composition can be suppressed, so that transfer molding can be performed with an improved moldability without any trouble. Further, the resin composition ensures improvement in soldering resistance and mechanical strength.

Abstract translation: 本发明涉及一种安全且优异的耐湿性，阻燃性和成型性的半导体封装树脂组合物以及通过用这种半导体封装树脂组合物包封半导体元件而制造的高可靠性半导体器件。 根据本发明的树脂组合物包含热固性树脂，硬化剂和由以下通式（1）表示的多面体晶体的复合金属氢氧化物：[其中M和Q是不同的金属元素; Q是属于周期表中选自IVa，Va，VIa，VIIa，VIII，Ib和IIb族的基团的金属元素; m，n，a，b，c，d和e可以相同或不同，各自表示正数]。 根据本发明，可以抑制树脂组合物的流动性的降低，从而可以在没有任何麻烦的情况下以改进的成型性进行传递模塑。 此外，树脂组合物确保了耐焊接性和机械强度的提高。

公开(公告)号：US06259114B1

公开(公告)日：2001-07-10

申请号：US09306635

申请日：1999-05-07

Applicant: James A. Misewich ,  Alejandro G. Schrott

Inventor： James A. Misewich ,  Alejandro G. Schrott

IPC: H01L2912

CPC classification number: H01L49/003

Abstract: A method and structure of forming an integrated circuit chip having a transistor includes forming a conductive oxide layer, forming a Mott transition oxide layer over the conductive oxide layer and forming an insulative oxide layer over the Mott transition oxide layer.

Abstract translation: 形成具有晶体管的集成电路芯片的方法和结构包括形成导电氧化物层，在导电氧化物层上形成Mott过渡氧化物层，并在Mott过渡氧化物层上形成绝缘氧化物层。