公开(公告)号：US20090061583A1

公开(公告)日：2009-03-05

申请号：US12250223

申请日：2008-10-13

Applicant: TING SING WANG

Inventor： TING SING WANG

IPC: H01L21/8242

CPC classification number: H01L29/7841 ,  H01L27/108 ,  H01L27/10802

Abstract: A method for preparing a dynamic random access memory structure, comprising steps of forming a bottom conductive region in a substrate, removing a predetermined portion of the substrate to form a plurality of pillars having a bottom end lower than a bottom surface of the bottom conductive region, forming a first oxide layer on the substrate and below the bottom conductive region in the pillar, forming a conductive block between two adjacent pillars to electrically connect the two bottom conductive regions in the two adjacent pillars, forming a second oxide layer covering the conductive block, forming a gate oxide layer on a sidewall of the pillar, forming a gate structure on a surface of the gate oxide layer; and forming an upper conductive region on a top portion of the pillar.

Abstract translation: 一种制备动态随机存取存储器结构的方法，包括以下步骤：在衬底中形成底部导电区域，去除衬底的预定部分以形成多个柱体，其底端低于底部导电区域的底表面 在所述基板上形成第一氧化物层并在所述柱的底部导电区域的下方形成第二氧化物层，在两个相邻的柱之间形成导电块以电连接所述两个相邻的柱中的两个底部导电区域，形成覆盖所述导电块的第二氧化物层 在所述柱的侧壁上形成栅极氧化层，在所述栅极氧化物层的表面上形成栅极结构; 以及在所述柱的顶部上形成上部导电区域。

公开(公告)号：US6010938A

公开(公告)日：2000-01-04

申请号：US192018

申请日：1998-11-11

Applicant: Ting-Sing Wang ,  Chon-Shin Jou ,  Kuan-Chou Sung

Inventor： Ting-Sing Wang ,  Chon-Shin Jou ,  Kuan-Chou Sung

IPC: H01L21/00

CPC classification number: H01L28/20 ,  H01L27/1112

Abstract: The present invention provides a new method for making a load resistor in a semiconductor chip. According to the new method, a linear-shaped doped polysilicon layer is formed onto the surface of the semiconductor chip that comprises a Si substrate and an NSG layer. This layer functions as a conductive path. A slot is formed in this layer by removing a section from the conductive path. This slot reaches down to the NSG layer effectively cutting off the polysilicon layer. Then, a rugged polysilicon layer is evenly deposited onto the surface of the slot for connection of the conductive path. The polysilicon layer over the slot and the doped polysilicon layer defines the load resistor. The result is a high resistance value with usage of only a small space.

Abstract translation: 本发明提供一种在半导体芯片中制造负载电阻的新方法。 根据新方法，在包括Si衬底和NSG层的半导体芯片的表面上形成线状掺杂多晶硅层。 该层用作导电路径。 通过从导电路径去除一部分，在该层中形成槽。 该槽向下到达NSG层，有效地切断了多晶硅层。 然后，将坚固的多晶硅层均匀地沉积到槽的表面上以连接导电路径。 槽上的多晶硅层和掺杂多晶硅层限定了负载电阻。 结果是具有仅较小空间的高电阻值。

公开(公告)号：US20080070371A1

公开(公告)日：2008-03-20

申请号：US11566761

申请日：2006-12-05

Applicant: Ting-Sing Wang

Inventor： Ting-Sing Wang

IPC: H01L21/336

CPC classification number: H01L29/1045 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor device includes a substrate, a gate electrode, a pair of first impurity regions, a pair of second impurity regions and at least one dummy pattern. The gate electrode is positioned above the substrate. The first impurity regions are positioned in the substrate and near both sides of the gate electrode. The second impurity regions are positioned in the first impurity regions respectively, and the dopant concentration of the first impurity regions is lower than the dopant concentration of the second impurity regions. The dummy pattern is positioned over the first impurity regions and exposes the second impurity regions.

Abstract translation: 半导体器件包括衬底，栅极电极，一对第一杂质区域，一对第二杂质区域和至少一个虚拟图案。 栅电极位于衬底上方。 第一杂质区位于基板中并靠近栅电极的两侧。 第二杂质区域分别位于第一杂质区域中，第一杂质区域的掺杂剂浓度低于第二杂质区域的掺杂剂浓度。 虚设图案位于第一杂质区上方并暴露第二杂质区。

公开(公告)号：US06774394B2

公开(公告)日：2004-08-10

申请号：US10061562

申请日：2002-02-01

Applicant: Ting-Sing Wang

Inventor： Ting-Sing Wang

IPC: H01L2358

CPC classification number: H01L21/76897 ,  H01L22/34

Abstract: The present invention provides an inline detection device for self-aligned contact defects, formed in a semiconductor substrate, comprising: an active area, formed in the semiconductor substrate, comprised of a serpentine gate having spacers on the side, a plurality of first contact windows nested immediately between the same spacers, a plurality of first contact plugs formed in the first contact windows, and two probing pads, formed in the semiconductor substrate, comprised of a plurality of matrix gates, a second contact window exposing portions of the matrix gates, and a second contact plug formed in the second contact window.

Abstract translation: 本发明提供了一种形成在半导体衬底中的自对准接触缺陷的在线检测装置，包括：形成在半导体衬底中的有源区，包括在侧面具有间隔物的蛇形栅极，多个第一接触窗口 立即嵌套在相同间隔件之间，形成在第一接触窗中的多个第一接触插塞和形成在半导体衬底中的两个探测焊盘，包括多个矩阵栅极，暴露矩阵栅极部分的第二接触窗口， 以及形成在第二接触窗口中的第二接触插塞。

公开(公告)号：US06677608B2

公开(公告)日：2004-01-13

申请号：US10004755

申请日：2001-12-03

Applicant: Ting-Sing Wang

Inventor： Ting-Sing Wang

IPC: H01L2912

CPC classification number: H01L22/34

Abstract: The present invention provides a semiconductor device for detecting gate defects and the method of using the same to detect gate defects. The semiconductor device is comprised of a semiconductor substrate having an oxide layer on the top, a gate having spacers, formed on the oxide layer and surrounding the semiconductor substrate, wherein the gate is also patterned to divide the semiconductor substrate into two parts not electrically connected, and a conductive layer formed on the semiconductor outside the gate. In addition, the method for using the semiconductor device of the present invention to detect gate defects is comprised of applying a ground voltage and a set voltage respectively to two parts divided by the gate in the semiconductor device, and measuring current between the two parts.

Abstract translation: 本发明提供一种用于检测栅极缺陷的半导体器件及其使用该方法来检测栅极缺陷。 半导体器件由在顶部具有氧化物层的半导体衬底，形成在氧化物层上并包围半导体衬底的间隔物的栅极组成，其中栅极也被图案化以将半导体衬底分成两个部分而不是电连接 以及形成在栅极外部的半导体上的导电层。 此外，使用本发明的半导体器件来检测栅极缺陷的方法包括分别将接地电压和设定电压施加到由半导体器件中的栅极划分的两个部分以及测量两个部分之间的电流。

公开(公告)号：US5824234A

公开(公告)日：1998-10-20

申请号：US725122

申请日：1996-10-02

Applicant: Chon-Shin Jou ,  Ting-Sing Wang ,  Chun-Lin Chen ,  Ming-Huan Tsai ,  Ming-Ru Tsai

Inventor： Chon-Shin Jou ,  Ting-Sing Wang ,  Chun-Lin Chen ,  Ming-Huan Tsai ,  Ming-Ru Tsai

IPC: H01L21/311 ,  H01L21/60 ,  H01L21/00

CPC classification number: H01L21/31138 ,  H01L24/03 ,  H01L2224/0381 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029

Abstract: The present invention provides a method for forming a bonding pad having a low contact resistance. The method includes steps of: a) forming a bonding pad structure on a substrate having a metal layer by forming a passivation layer over said metal layer and etching the passivation layer with a fluorine-containing gas by which a fluorine-containing layer is formed on a surface of said bonding pad structure; and b) removing the fluorine-containing layer for reducing a contact resistance of said bonding pad structure.

Abstract translation: 本发明提供一种形成接触电阻低的焊盘的方法。 该方法包括以下步骤：a）在具有金属层的衬底上形成焊盘结构，在所述金属层上形成钝化层，并用形成含氟层的含氟气体蚀刻钝化层 所述焊盘结构的表面; 以及b）除去所述含氟层以降低所述接合焊盘结构的接触电阻。

公开(公告)号：US07622352B2

公开(公告)日：2009-11-24

申请号：US11440075

申请日：2006-05-25

Applicant: Ting Sing Wang

Inventor： Ting Sing Wang

IPC: H01L21/336

CPC classification number: H01L29/1037 ,  H01L21/28114 ,  H01L21/28141 ,  H01L29/1045 ,  H01L29/42376 ,  H01L29/66659

Abstract: A multi-step gate structure comprises a semiconductor substrate having a multi-step structure, a gate oxide layer positioned on the multi-step structure and a conductive layer positioned on the gate oxide layer. Preferably, the gate oxide layer has different thicknesses on each step surface of the multi-step structure. In addition, the multi-step gate structure further comprises a plurality of doped regions positioned in the semiconductor substrate under the multi-step structure. The channel length of the multi-step gate structure is the summation of the lateral width and the vertical depth of the multi-step gate structure, which is dramatically increased such that problems originated from the short channel effect can be effectively solved. Further, the plurality of doped regions under the multi-step structure are prepared by implanting processes having different dosages and dopants, which can control the thickness of the gate oxide layer and the threshold voltage of the multi-step gate structure.

Abstract translation: 多级栅极结构包括具有多级结构的半导体衬底，位于多级结构上的栅极氧化物层和位于栅极氧化物层上的导电层。 优选地，栅极氧化物层在多步骤结构的每个台阶表面上具有不同的厚度。 此外，多步栅极结构还包括在多步结构下定位在半导体衬底中的多个掺杂区域。 多级栅极结构的沟道长度是多级栅极结构的横向宽度和垂直深度的总和，其显着增加，从而可以有效地解决源自短沟道效应的问题。 此外，通过注入具有不同剂量和掺杂剂的工艺来制备多步结构下的多个掺杂区域，其可以控制栅极氧化物层的厚度和多步栅极结构的阈值电压。

公开(公告)号：US07319058B2

公开(公告)日：2008-01-15

申请号：US11161724

申请日：2005-08-15

Applicant: Ting-Sing Wang

Inventor： Ting-Sing Wang

IPC: H01L21/336

CPC classification number: H01L29/7923 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7926

Abstract: A fabrication method for a non-volatile memory is provided. To fabricate the non-volatile memory, a plurality of first trenches and second trenches are formed in a substrate, wherein the second trenches are disposed above the first trenches and cross over the first trenches. Then, a tunneling layer and a charge storage layer are sequentially formed on both sidewalls of each second trench. An isolation layer is filled into the first trench. Furthermore, a charge barrier layer is formed on the sidewall of the second trench, and a gate dielectric layer is formed at the bottom of the second trench. A control gate layer is filled into the second trench. Finally, two first doping regions are formed in the substrate at both sides of the control gate layer.

Abstract translation: 提供了一种用于非易失性存储器的制造方法。 为了制造非易失性存储器，在衬底中形成多个第一沟槽和第二沟槽，其中第二沟槽设置在第一沟槽上方并跨过第一沟槽。 然后，在每个第二沟槽的两个侧壁上依次形成隧穿层和电荷存储层。 隔离层被填充到第一沟槽中。 此外，在第二沟槽的侧壁上形成电荷阻挡层，在第二沟槽的底部形成栅极电介质层。 控制栅极层被填充到第二沟槽中。 最后，在控制栅极层两侧的衬底中形成两个第一掺杂区。

公开(公告)号：US07557407B2

公开(公告)日：2009-07-07

申请号：US11435848

申请日：2006-05-18

Applicant: Ting Sing Wang

Inventor： Ting Sing Wang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/42368 ,  H01L21/28141 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/7834

Abstract: A recessed gate structure comprises a semiconductor substrate, a recess positioned in the semiconductor substrate, a gate oxide layer positioned in the recess and a conductive layer positioned on the gate oxide layer, wherein the semiconductor substrate has a multi-step structure in the recess. The thickness of the gate oxide layer on one step surface can be different from that on another step surface of the multi-step structure. In addition, the recessed gate structure further comprises a plurality of doped regions positioned in the semiconductor substrate under the multi-step structure, and these doped regions may use different dosages and different types of dopants. There is a carrier channel in the semiconductor substrate under the recessed gate structure and the overall channel length of the carrier channel is substantially the summation of the lateral width and twice of the vertical depth of the recessed gate structure.

Abstract translation: 凹陷栅极结构包括半导体衬底，位于半导体衬底中的凹部，位于凹槽中的栅极氧化物层和位于栅极氧化物层上的导电层，其中半导体衬底在凹部中具有多级结构。 一步表面上的栅极氧化层的厚度可以与多步结构的另一台阶表面上的厚度不同。 此外，凹陷栅极结构还包括在多步结构下定位在半导体衬底中的多个掺杂区域，并且这些掺杂区域可以使用不同的剂量和不同类型的掺杂剂。 在凹陷栅极结构下方的半导体衬底中存在载流子通道，并且载流子通道的整体沟道长度基本上是凹入栅极结构的横向宽度和垂直深度的两倍的总和。

公开(公告)号：US07456458B2

公开(公告)日：2008-11-25

申请号：US11402871

申请日：2006-04-13

Applicant: Ting Sing Wang

Inventor： Ting Sing Wang

IPC: H01L27/108

CPC classification number: H01L29/7841 ,  H01L27/108 ,  H01L27/10802

Abstract: A dynamic random access memory structure having a vertical floating body cell includes a semiconductor substrate having a plurality of cylindrical pillars, an upper conductive region positioned on a top portion of the cylindrical pillar, a body positioned below the upper conductive portion in the cylindrical pillar, a bottom conductive portion positioned below the body in the cylindrical pillar, a gate oxide layer surrounding the sidewall of the cylindrical pillar and a gate structure surrounding the gate oxide layer. The upper conductive region serves as a drain electrode, the bottom conductive region serves as a source electrode and the body can store carriers such as holes. Preferably, the dynamic random access memory structure further comprises a conductive layer positioned on the surface of the semiconductor substrate to electrically connect the bottom conductive regions in the cylindrical pillars.

Abstract translation: 具有垂直浮体单元的动态随机存取存储器结构包括具有多个圆柱形柱状物的半导体衬底，位于圆柱形柱体顶部的上部导电区域，位于圆柱形柱体中的上部导电部分下方的主体， 位于圆柱形柱体的主体下方的底部导电部分，围绕圆柱形柱的侧壁的栅极氧化物层和围绕栅极氧化物层的栅极结构。 上导电区域用作漏电极，底部导电区域用作源电极，并且主体可以存储诸如孔的载体。 优选地，动态随机存取存储器结构还包括位于半导体衬底的表面上的导电层，以电连接圆柱形支柱中的底部导电区域。