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    ENHANCING ADHESION OF INTERLAYER DIELECTRIC MATERIALS OF SEMICONDUCTOR DEVICES BY SUPPRESSING SILICIDE FORMATION AT THE SUBSTRATE EDGE
    1.
    发明申请
    ENHANCING ADHESION OF INTERLAYER DIELECTRIC MATERIALS OF SEMICONDUCTOR DEVICES BY SUPPRESSING SILICIDE FORMATION AT THE SUBSTRATE EDGE 有权
    通过在基板边缘抑制硅化物形成来增强半导体器件的中间层介电材料的粘合

    公开(公告)号：US20100248463A1

    公开(公告)日：2010-09-30

    申请号：US12749890

    申请日：2010-03-30

    申请人： Tobias Letz ,  Frank Feustel ,  Kai Frohberg

    发明人： Tobias Letz ,  Frank Feustel ,  Kai Frohberg

    IPC分类号： H01L21/31 ,  H01L21/28 ,  H01L21/3205

    CPC分类号： H01L29/665 ,  H01L21/02087 ,  H01L29/7833

    摘要： Adhesion of dielectric layer stacks to be formed after completing the basic configuration of transistor elements may be increased by avoiding the formation of a metal silicide in the edge region of the substrate. For this purpose, a dielectric protection layer may be selectively formed in the edge region prior to a corresponding pre-clean process or immediately prior to deposition of the refractory metal. Hence, non-reacted metal may be efficiently removed from the edge region without creating a non-desired metal silicide. Hence, the further processing may be continued on the basis of enhanced process conditions for forming interlayer dielectric materials.

    摘要翻译： 在完成晶体管元件的基本结构之后形成的电介质层叠层的粘附可以通过避免在衬底的边缘区域中形成金属硅化物来增加。 为此目的，可以在相应的预清洁工艺之前或刚好在沉积难熔金属之前，在边缘区域中选择性地形成绝缘保护层。 因此，可以从边缘区域有效地除去未反应的金属，而不产生不需要的金属硅化物。 因此，可以基于用于形成层间电介质材料的增强的工艺条件来继续进一步的处理。

    Enhancing adhesion of interlayer dielectric materials of semiconductor devices by suppressing silicide formation at the substrate edge
    2.
    发明授权
    Enhancing adhesion of interlayer dielectric materials of semiconductor devices by suppressing silicide formation at the substrate edge 有权
    通过抑制衬底边缘处的硅化物形成来增强半导体器件的层间电介质材料的附着力

    公开(公告)号：US08859398B2

    公开(公告)日：2014-10-14

    申请号：US12749890

    申请日：2010-03-30

    申请人： Tobias Letz ,  Frank Feustel ,  Kai Frohberg

    发明人： Tobias Letz ,  Frank Feustel ,  Kai Frohberg

    IPC分类号： H01L21/78 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

    CPC分类号： H01L29/665 ,  H01L21/02087 ,  H01L29/7833

    摘要： Adhesion of dielectric layer stacks to be formed after completing the basic configuration of transistor elements may be increased by avoiding the formation of a metal silicide in the edge region of the substrate. For this purpose, a dielectric protection layer may be selectively formed in the edge region prior to a corresponding pre-clean process or immediately prior to deposition of the refractory metal. Hence, non-reacted metal may be efficiently removed from the edge region without creating a non-desired metal silicide. Hence, the further processing may be continued on the basis of enhanced process conditions for forming interlayer dielectric materials.

    摘要翻译： 在完成晶体管元件的基本结构之后形成的电介质层叠层的粘附可以通过避免在衬底的边缘区域中形成金属硅化物来增加。 为此目的，可以在相应的预清洁工艺之前或刚好在沉积难熔金属之前，在边缘区域中选择性地形成绝缘保护层。 因此，可以从边缘区域有效地除去未反应的金属，而不产生不需要的金属硅化物。 因此，可以基于用于形成层间电介质材料的增强的工艺条件来继续进一步的处理。

    Local silicidation of via bottoms in metallization systems of semiconductor devices
    4.
    发明授权
    Local silicidation of via bottoms in metallization systems of semiconductor devices 有权
    半导体器件金属化系统中通孔底部的局部硅化

    公开(公告)号：US08193086B2

    公开(公告)日：2012-06-05

    申请号：US12640444

    申请日：2009-12-17

    申请人： Tobias Letz ,  Frank Feustel

    发明人： Tobias Letz ,  Frank Feustel

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76814 ,  H01L21/76826 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76886

    摘要： Electromigration behavior in complex metallization systems of semiconductor devices may be enhanced at critical areas between a metal line and a via by locally forming a copper/silicon compound. In some illustrative embodiments, the formation of the copper/silicon compound may be combined with other treatments for cleaning the exposed surface areas and/or modifying the molecular structure thereof.

    摘要翻译： 通过局部形成铜/硅化合物，可以在金属线和通孔之间的关键区域增强半导体器件复杂金属化系统中的电迁移行为。 在一些说明性实施例中，铜/硅化合物的形成可以与用于清洁暴露的表面区域和/或改变其分子结构的其它处理组合。

    TEST SYSTEM AND METHOD OF REDUCING DAMAGE IN SEED LAYERS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES
    5.
    发明申请
    TEST SYSTEM AND METHOD OF REDUCING DAMAGE IN SEED LAYERS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES 有权
    在半导体器件金属化系统中减少种植层损伤的测试系统和方法

    公开(公告)号：US20100244028A1

    公开(公告)日：2010-09-30

    申请号：US12749805

    申请日：2010-03-30

    申请人： Frank Feustel ,  Tobias Letz ,  Frank Koschinsky

    发明人： Frank Feustel ,  Tobias Letz ,  Frank Koschinsky

    IPC分类号： H01L21/768 ,  H01L23/544

    CPC分类号： H01L22/12 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

    摘要： During the formation of a complex metallization system, the influence of a manufacturing environment on sensitive barrier/seed material systems may be monitored or controlled by using an appropriate test pattern and applying an appropriate test strategy. For example, actual probe and reference substrates may be prepared and may be processed with and without exposure to the manufacturing environment of interest, thereby enabling an efficient evaluation of one or more parameters of the environment. Furthermore, an “optimized” manufacturing environment may be obtained on the basis of the test strategy disclosed herein.

    摘要翻译： 在形成复杂的金属化系统期间，可以通过使用适当的测试图案并应用适当的测试策略来监测或控制制造环境对敏感屏障/种子材料系统的影响。 例如，可以制备实际的探针和参考基底并且可以在不暴露于感兴趣的制造环境的情况下进行处理，从而能够有效评估环境的一个或多个参数。 此外，可以基于本文公开的测试策略获得“优化的”制造环境。

    LOCAL SILICIDATION OF VIA BOTTOMS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES
    6.
    发明申请
    LOCAL SILICIDATION OF VIA BOTTOMS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES 有权
    在半导体器件金属化系统中通过底部的局部硅化

    公开(公告)号：US20100164123A1

    公开(公告)日：2010-07-01

    申请号：US12640444

    申请日：2009-12-17

    申请人： Tobias Letz ,  Frank Feustel

    发明人： Tobias Letz ,  Frank Feustel

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L21/76814 ,  H01L21/76826 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76886

    摘要： Electromigration behavior in complex metallization systems of semiconductor devices may be enhanced at critical areas between a metal line and a via by locally forming a copper/silicon compound. In some illustrative embodiments, the formation of the copper/silicon compound may be combined with other treatments for cleaning the exposed surface areas and/or modifying the molecular structure thereof.

    摘要翻译： 通过局部形成铜/硅化合物，可以在金属线和通孔之间的关键区域增强半导体器件复杂金属化系统中的电迁移行为。 在一些说明性实施例中，铜/硅化合物的形成可以与用于清洁暴露的表面区域和/或改变其分子结构的其它处理组合。

    Test system and method of reducing damage in seed layers in metallization systems of semiconductor devices
    8.
    发明授权
    Test system and method of reducing damage in seed layers in metallization systems of semiconductor devices 有权
    减少半导体器件金属化系统种子层损伤的试验系统和方法

    公开(公告)号：US08323989B2

    公开(公告)日：2012-12-04

    申请号：US12749805

    申请日：2010-03-30

    申请人： Frank Feustel ,  Tobias Letz ,  Frank Koschinsky

    发明人： Frank Feustel ,  Tobias Letz ,  Frank Koschinsky

    IPC分类号： H01L21/66 ,  H01L23/58

    CPC分类号： H01L22/12 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

    摘要： During the formation of a complex metallization system, the influence of a manufacturing environment on sensitive barrier/seed material systems may be monitored or controlled by using an appropriate test pattern and applying an appropriate test strategy. For example, actual probe and reference substrates may be prepared and may be processed with and without exposure to the manufacturing environment of interest, thereby enabling an efficient evaluation of one or more parameters of the environment. Furthermore, an “optimized” manufacturing environment may be obtained on the basis of the test strategy disclosed herein.

    摘要翻译： 在形成复杂的金属化系统期间，可以通过使用适当的测试图案并应用适当的测试策略来监测或控制制造环境对敏感屏障/种子材料系统的影响。 例如，可以制备实际的探针和参考基底并且可以在不暴露于感兴趣的制造环境的情况下进行处理，从而能够有效评估环境的一个或多个参数。 此外，可以基于本文公开的测试策略获得优化的制造环境。

    METHOD AND TEST STRUCTURE FOR ESTIMATING ELECTROMIGRATION EFFECTS CAUSED BY POROUS BARRIER MATERIALS
    9.
    发明申请
    METHOD AND TEST STRUCTURE FOR ESTIMATING ELECTROMIGRATION EFFECTS CAUSED BY POROUS BARRIER MATERIALS 审中-公开
    估计多孔障碍物材料引起的电化学效应的方法与试验结构

    公开(公告)号：US20070278484A1

    公开(公告)日：2007-12-06

    申请号：US11626705

    申请日：2007-01-24

    申请人： Frank Feustel ,  Christine Hau-Riege ,  Tobias Letz

    发明人： Frank Feustel ,  Christine Hau-Riege ,  Tobias Letz

    IPC分类号： H01L23/58 ,  H01L21/66

    CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： By providing a test structure for electromigration tests in semiconductor devices, which may indicate the status of a barrier layer at the bottom of a test via in the structure, a significantly increased reliability of respective electromigration tests may be obtained. Furthermore, the degree of porosity of the barrier layer may be estimated on the basis of the resulting test structure, which comprises a feed line having an increased probability for void formation compared to the test via, when a specific degree of porosity is created in the test via.

    摘要翻译： 通过提供用于半导体器件中的电迁移测试的测试结构，其可以指示在结构中的测试通孔底部的阻挡层的状态，可以获得相应的电迁移测试的显着提高的可靠性。 此外，可以基于所得到的测试结构来估计阻挡层的孔隙率，该测试结构包括与测试孔相比具有增加的空隙形成概率的进料线，当在 通过测试。