公开(公告)号：US20100139406A1

公开(公告)日：2010-06-10

申请号：US12569691

申请日：2009-09-29

申请人： Todd H. Stievater ,  William S. Rabinovich ,  Nicolas A. Papanicolaou ,  Robert Bass ,  Jennifer L. Stepnowski ,  R. Andrew McGill

发明人： Todd H. Stievater ,  William S. Rabinovich ,  Nicolas A. Papanicolaou ,  Robert Bass ,  Jennifer L. Stepnowski ,  R. Andrew McGill

IPC分类号： G01N29/00

CPC分类号： G01N29/036 ,  G01N2291/0256

摘要： Micro-opto-mechanical chemical sensors and methods for simultaneously detecting and discriminating between a variety of vapor-phase analytes. One embodiment of the sensor is a photonic microharp chemical sensor with an array of closely spaced microbridges, each differing slightly in length and coated with a different sorbent polymer. The microbridges can be excited photothermally, and the microbridges can be optically interrogated using microcavity interferometry. Other actuation methods include piezoelectric, piezoresistive, electrothermal, and magnetic. Other read-out techniques include using a lever arm and other interferometric techniques.

摘要翻译： 微光机械化学传感器和同时检测和区分各种气相分析物的方法。 传感器的一个实施例是具有紧密间隔的微桥阵列的光子微量化学传感器，每个微桥长度略微不同，并涂覆有不同的吸附剂聚合物。 微桥可以光热激发，微桥可以使用微腔干涉法进行光学询问。 其他致动方法包括压电，压阻，电热和磁性。 其他读出技术包括使用杠杆臂和其他干涉测量技术。

公开(公告)号：US4611140A

公开(公告)日：1986-09-09

申请号：US769099

申请日：1985-08-26

申请人： Robert R. Whitlock ,  Nicolas A. Papanicolaou

发明人： Robert R. Whitlock ,  Nicolas A. Papanicolaou

IPC分类号： H03H9/02 ,  H01L41/08

CPC分类号： H03H9/02976

摘要： A line imager comprising: a semiconductor body; a planar, transparent piezoelectric body having a main surface overlying and in proximity to the semiconductor body; wave propagation means for propagating acoustic waves on the main surface of the piezoelectric body to create traveling potential wells in the underlying semiconductor body; a traveling potential well path located in the semiconductor, the traveling potential well path beginning at the wave propogation means and extending straight away therefrom; semiconductor depletion means for depleting the semiconductor of majority charge carriers along the traveling potential well path, the depletion means located atop the piezoelectric body; a gate located on the semiconductor body and alongside and parallel to the traveling potential well path and adjoining the semiconductor depletion means; a plurality of sensor pixels for accumulating charge, the sensor pixels located in the semiconductor body, the pixels aligned next to each other and running parallel to, alongside and overlapping the gate so the integrated charge in each sensor pixel will proceed into their respective traveling potential wells when the potential across the gate is lowered, the gate having length at least equal to the length of the plurality of sensor pixels; and a dump gate located on the semiconductor and parallel to and overlapping the plurality of sensor pixels, the plurality of sensor pixels being situated between the dump gate and the gate, the dump gate causing the charge integrated in the plurality of sensor pixels to flow to ground when the potential across the dump gate is lowered, the dump gate being at least as long as the length of the plurality of sensor pixels.

摘要翻译： 一种线成像器，包括：半导体本体; 平面的透明的压电体，其具有覆盖并接近半导体本体的主表面; 波传播装置，用于在压电体的主表面上传播声波，以在下面的半导体本体中产生行进势阱; 位于半导体中的行进电位阱路径，从波浪传播装置开始并从其延伸的行进电位阱路径; 半导体耗尽装置，用于消耗沿着行进势阱路径的多数电荷载流子的半导体，所述耗尽装置位于压电体的顶部; 位于所述半导体主体上并与所述行进电位井路径并列并且邻接所述半导体耗尽装置的栅极; 用于累积电荷的多个传感器像素，位于半导体本体中的传感器像素，像素彼此排列并行并行并且与栅极重叠，使得每个传感器像素中的积分电荷将进入它们各自的行进电位 当栅极两端的电位降低时，栅极的长度至少等于多个传感器像素的长度; 位于所述半导体上并且与所述多个传感器像素平行且重叠的倾倒门，所述多个传感器像素位于所述倾倒门和所述门之间，所述倾倒门引起所述多个传感器像素中集成的电荷流向 当转储门的电位降低时，转储门至少与多个传感器像素的长度一样长。

公开(公告)号：US4600853A

公开(公告)日：1986-07-15

申请号：US768651

申请日：1985-08-23

申请人： Robert R. Whitlock ,  Nicolas A. Papanicolaou

发明人： Robert R. Whitlock ,  Nicolas A. Papanicolaou

IPC分类号： H03H9/02 ,  H03H15/02 ,  H01L41/08

CPC分类号： H03H9/02976

摘要： A device for the high speed recording of photon images and nonrepetitive electrical waveforms which comprises a waveform recorder wherein surface acoustic waves excited in a can be GaAs, not layered piezoelectric-insulator-semiconductor layered structure produce a traveling electric field in the semiconductor substrate. Charges stored in the traveling potential wells and representing the instantaenous amplitude of a waveform to be recorded are transferred at static wells when a gate is dropped. Because each successive traveling well represents a different time instant of the waveform, the different spatial locations of the static wells correspond to different times. The output signal from the static wells can be selectively delayed before application to a display oscilloscope to enable display of the waveform at a rate many times slower than the actual frequency of the signal waveform.

摘要翻译： 用于高速记录光子图像和非重复性电波形的装置，其包括波形记录器，其中在其中激发的表面声波可以是GaAs，而不是分层的压电绝缘体 - 半导体层状结构在半导体衬底中产生行进电场。 存储在行进电位井中并表示要记录的波形的瞬时振幅的电荷在静电井下降时被传送。 由于每个连续行进井表示波形的不同时刻，静态井的不同空间位置对应于不同的时间。 来自静态阱的输出信号可以在应用于显示示波器之前被选择性地延迟，以使波形以比信号波形的实际频率慢许多倍的速率显示。

公开(公告)号：US5103280A

公开(公告)日：1992-04-07

申请号：US212841

申请日：1988-06-29

申请人： Phillip E. Thompson ,  Nicolas A. Papanicolaou ,  J. Bradley Boos

发明人： Phillip E. Thompson ,  Nicolas A. Papanicolaou ,  J. Bradley Boos

IPC分类号： H01L31/0304 ,  H01L31/09

CPC分类号： H01L31/03042 ,  H01L31/09 ,  Y02E10/544

摘要： A photoconductive semiconductor device having a source, a drain, and a photosensitive channel therebetween. The channel has a surface layer that is highly doped with respect to the remainder of the channel, compensating at least in part for the channel's surface depletion layer. In this manner, the photosensitivity of the device is increased without disproportionately increasing wasted dark current. In a preferred embodiment, the additional doping of the channel's surface layer is done by ion implantation, and the device is a monolith formed of gallium arsenide.

摘要翻译： 一种光电导半导体器件，其间具有源极，漏极和光敏通道。 通道具有相对于沟道的其余部分高度掺杂的表面层，至少部分补偿沟道的表面耗尽层。 以这种方式，增加器件的光敏性而不会不利地增加浪费的暗电流。 在优选实施例中，通过离子注入来实现沟道表面层的附加掺杂，并且器件是由砷化镓形成的整体。

公开(公告)号：US4924285A

公开(公告)日：1990-05-08

申请号：US262765

申请日：1988-10-25

申请人： Gordon W. Anderson ,  John B. Boos ,  Harry B. Dietrich ,  David I. Ma ,  Ingham A. G. Mack ,  Nicolas A. Papanicolaou

发明人： Gordon W. Anderson ,  John B. Boos ,  Harry B. Dietrich ,  David I. Ma ,  Ingham A. G. Mack ,  Nicolas A. Papanicolaou

IPC分类号： H01L27/144

CPC分类号： H01L27/1446

摘要： An integrated, planar, single-channel, photodetector-amplifier device is disclosed. The single-channel device includes a photodetector layer and an amplifier layer above the photodetector layer. The photodetector layer is low-doped to give a low dark current and is sufficiently thick to give a high quantum efficiency. The amplifier layer is of a smaller thickness and is a more highly doped material than the photodetector layer, to provide an amplifier having high gain. An insulating layer is included between the photodetector and amplifier layers for electrically isolating the photodetector and amplifier layers. The layers are fabricated on a substrate. Isolation regions are also included for electrically laterally isolating a photodetector, amplifier, and other circuit components comprising the single channel device from each other.An integrated multi-channel photodetector-amplifier array is also disclosed which array comprises a plurality of single-channel photodetector-amplifier devices fabricated on the same substrate with isolation regions created by proton bombardment to electrically laterally isolate the individual circuit channels from each other. The photodetector-amplifier array may be a linear or an area array.

摘要翻译： 公开了一种集成的平面单通道光电检测放大器装置。 单通道器件包括光电检测器层和光电检测器层上方的放大器层。 光电检测器层是低掺杂的以产生低暗电流并且足够厚以产生高量子效率。 放大器层具有较小的厚度，并且是比光电检测器层更高掺杂的材料，以提供具有高增益的放大器。 在光电检测器和放大器层之间包括绝缘层，用于电隔离光电检测器和放大器层。 在衬底上制造这些层。 还包括用于将包括单通道器件的光电检测器，放大器和其它电路部件电横向隔离的隔离区域。 还公开了一种集成的多通道光电检测器 - 放大器阵列，其阵列包括在同一衬底上制造的多个单通道光电检测器 - 放大器器件，其具有由质子轰击产生的隔离区域，以将各个电路通道彼此电横向隔离。 光电检测器 - 放大器阵列可以是线性或区域阵列。

公开(公告)号：US5015603A

公开(公告)日：1991-05-14

申请号：US291479

申请日：1988-12-28

申请人： John B. Boos ,  Nicolas A. Papanicolaou ,  Tung H. Weng

发明人： John B. Boos ,  Nicolas A. Papanicolaou ,  Tung H. Weng

IPC分类号： H01L29/45

CPC分类号： H01L29/452

摘要： A low metal resistance ohmic contact alloyed to p InP material having TiW within the contact as a diffusion barrier layer between an underlay of AuZn and an overlay of Au. A process for fabricating an InP JFET containing a gate contact of respective AuZn, TiW, and Au layers and with the gate contact alloyed to p InP material of a semiconductive gate region provides an improved InP JFET having a low resistance metal alloyed ohmic contact to the gate region. Use of the TiW layer in a multilayer contact alloyed to P InP material leads to unique processing and improved InP semiconductor devices.

摘要翻译： 一种低金属电阻欧姆接触，与接触中具有TiW的p InP材料合金化，作为AuZn衬底和Au覆盖层之间的扩散阻挡层。 制造包含各自AuZn，TiW和Au层的栅极接触以及与半导体栅极区域的pInP材料合金化的栅极接触的InP JFET的工艺提供了一种改进的InP JFET，其具有低电阻金属合金欧姆接触 门区域。 在与P InP材料合金化的多层接触中使用TiW层导致独特的加工和改进的InP半导体器件。

公开(公告)号：US4481082A

公开(公告)日：1984-11-06

申请号：US440783

申请日：1982-11-10

申请人： Nicolas A. Papanicolaou

发明人： Nicolas A. Papanicolaou

IPC分类号： B23P13/04 ,  C04B41/45 ,  C04B41/52 ,  C04B41/81 ,  C04B41/89 ,  H01L21/48 ,  C25D5/34

CPC分类号： C04B41/009 ,  B23P13/04 ,  C04B41/4572 ,  C04B41/52 ,  C04B41/81 ,  C04B41/89 ,  H01L21/4807 ,  Y10T29/49812

摘要： A method of making rings which includes the steps of placing tubes into a container, filling the container with a bonding material in liquid form, solidifying the bonding material within the container, slicing the container into wafers and then removing the bonding material from the wafers leaving the rings as a residual product. The wafers can also be metalized in order to metalize the upper and lower faces of the rings embedded therein.

摘要翻译： 一种制造环的方法，其包括以下步骤：将管放置在容器中，用液体形式的接合材料填充容器，固化容器内的粘合材料，将容器切成晶片，然后从晶片上移除粘合材料，离开晶片 戒指作为残留产品。 也可以将晶片金属化以使嵌入其中的环的上表面和下表面金属化。

公开(公告)号：US4425195A

公开(公告)日：1984-01-10

申请号：US440784

申请日：1982-11-10

申请人： Nicolas A. Papanicolaou

发明人： Nicolas A. Papanicolaou

IPC分类号： H01L21/48 ,  H01L23/373 ,  C25D1/20 ,  C25D5/02 ,  C25D5/12

CPC分类号： H01L21/4803 ,  H01L23/3732 ,  H01L2924/0002

摘要： A method of fabricating a diamond heat sink which includes the steps of metalizing a diamond, temporarily attaching the diamond to a base plate, electroplating the exposed surfaces of the diamond with at least a primary metallic layer to provide a metallic base, and separating the base plate from the diamond thereby leaving the diamond heat sink.

摘要翻译： 一种制造金刚石散热器的方法，其包括将金刚石金属化，临时将金刚石附着到基板上的步骤，用至少一个金属层电镀金刚石的暴露表面以提供金属基底，以及分离基底 从金刚石板上离开金刚石散热片。

公开(公告)号：US20130149845A1

公开(公告)日：2013-06-13

申请号：US13756566

申请日：2013-02-01

申请人： Brian R. Bennett ,  John Bradley Boos ,  Mario Ancona ,  James G. Champlain ,  Nicolas A. Papanicolaou

发明人： Brian R. Bennett ,  John Bradley Boos ,  Mario Ancona ,  James G. Champlain ,  Nicolas A. Papanicolaou

IPC分类号： H01L21/02

CPC分类号： H01L21/02398 ,  H01L21/02395 ,  H01L21/02466 ,  H01L21/02505 ,  H01L21/02549 ,  H01L27/0605

摘要： A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of a heterostructure that includes a Te-delta doped AlyGa1-ySb layer above the InxGa1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlyGa1-ySb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlyGa1-ySb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InxGa1-xSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.

摘要翻译： 在同一器件中单个In x Ga 1-x Sb量子阱用作n沟道和p沟道的互补金属氧化物半导体（CMOS）器件及其制造方法。 In x Ga 1-x Sb层是异质结构的一部分，其在结构的一部分上包括在In x Ga 1-x Sb层上方的Te-δ掺杂的Al y Ga 1-y Sb。 可以通过使用适当的源极，栅极和漏极端子将不具有Te-δ掺杂的AlI y Ga 1-y Sb阻挡层的部分结构制成p-FET，并且保留Te-δ掺杂的Al y Ga 1 -ySb层可以制造成n-FET，使得该结构形成CMOS器件，其中单个In x Ga 1-x Sb量子阱用作异质结构的n-FET部分和p-FET部分的传输沟道。

公开(公告)号：US20110297916A1

公开(公告)日：2011-12-08

申请号：US13115453

申请日：2011-05-25

申请人： Brian R. Bennett ,  John Bradley Boos ,  Mario Ancona ,  James G. Champlain ,  Nicolas A. Papanicolaou

发明人： Brian R. Bennett ,  John Bradley Boos ,  Mario Ancona ,  James G. Champlain ,  Nicolas A. Papanicolaou

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/02398 ,  H01L21/02395 ,  H01L21/02466 ,  H01L21/02505 ,  H01L21/02549 ,  H01L27/0605

摘要： A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of a heterostructure that includes a Te-delta doped AlyGa1-ySb layer above the InxGa1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlyGa1-ySb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlyGa1-ySb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InxGa1-xSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.

摘要翻译： 在同一器件中单个In x Ga 1-x Sb量子阱用作n沟道和p沟道的互补金属氧化物半导体（CMOS）器件及其制造方法。 In x Ga 1-x Sb层是异质结构的一部分，其在结构的一部分上包括在In x Ga 1-x Sb层上方的Te-δ掺杂的Al y Ga 1-y Sb。 可以通过使用适当的源极，栅极和漏极端子将不具有Te-δ掺杂的AlI y Ga 1-y Sb阻挡层的部分结构制成p-FET，并且保留Te-δ掺杂的Al y Ga 1 -ySb层可以制造成n-FET，使得该结构形成CMOS器件，其中单个In x Ga 1-x Sb量子阱用作异质结构的n-FET部分和p-FET部分的传输沟道。