利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

82 条记录 (耗时 0.032 秒)

    Digital signal processing system for parallel processing of subsampled data
    1.
    发明授权
    Digital signal processing system for parallel processing of subsampled data 失效
    用于并行处理子采样数据的数字信号处理系统

    公开(公告)号：US5130797A

    公开(公告)日：1992-07-14

    申请号：US483840

    申请日：1990-02-23

    申请人： Tokumichi Murakami ,  Koh Kamizawa ,  Hideo Ohira ,  Kohji Ogura ,  Naoto Kinjo ,  Takao Wakabayashi

    发明人： Tokumichi Murakami ,  Koh Kamizawa ,  Hideo Ohira ,  Kohji Ogura ,  Naoto Kinjo ,  Takao Wakabayashi

    IPC分类号： H04N7/26 ,  H04N7/36 ,  H04N7/46

    CPC分类号： H04N19/00 ,  H04N19/43 ,  H04N19/436 ,  H04N19/51 ,  H04N19/533 ,  H04N19/577 ,  H04N19/587 ,  H04N19/30

    摘要： A video codec system inputs consecutively frame after frame of sub-sampled video data obtained by sub-sampling video data in units of frames. The video data is coded in parallel by internal coding circuits. This averages the numbers of significant pixels in the sub-sampled video data to be processed. The coded video data is composed so as to comply with specifications of the receiving equipment. Upon transmission, the data is again sub-sampled depending on the number of coding circuits on the receiving side. Each piece of the sub-sampled data is given a header for consecutive transmission. This allows for a certain period of time between pieces of data that arrive at the receiving side, thereby eliminating time differences in receiving and coding.

    摘要翻译： 视频编解码器系统以帧为单位对视频数据进行子采样而获得的子采样视频数据的帧后连续输入。 视频数据由内部编码电路并行编码。 这将对待处理的子采样视频数据中的有效像素数进行平均。 编码视频数据被构成为符合接收设备的规格。 在发送时，根据接收侧的编码电路的数量再次对数据进行子采样。 给每个子采样数据提供连续传输的报头。 这允许在到达接收侧的数据段之间的一定时间段，从而消除接收和编码中的时间差异。

    Address control and generating system for digital signal-processor
    3.
    发明授权
    Address control and generating system for digital signal-processor 失效
    数字信号处理器的地址控制和发生系统

    公开(公告)号：US5206940A

    公开(公告)日：1993-04-27

    申请号：US750512

    申请日：1991-08-27

    申请人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

    发明人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

    IPC分类号： G06F7/575 ,  G06F9/32 ,  G06F9/355 ,  G06F9/38 ,  G06F13/28 ,  G06F15/78

    CPC分类号： G06F7/575 ,  G06F13/28 ,  G06F15/7832 ,  G06F15/7842 ,  G06F15/786 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/355 ,  G06F9/3877 ,  G06F9/3885 ,  G06F2207/3884

    摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

    摘要翻译： 一种简单的电路配置的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。 数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线， 地址产生单元，其能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元 执行阶段

    Digital signal processor system having host processor for writing instructions into internal processor memory
    4.
    发明授权
    Digital signal processor system having host processor for writing instructions into internal processor memory 失效
    数字信号处理器系统具有用于将指令写入内部处理器存储器的主处

    公开(公告)号：US5237667A

    公开(公告)日：1993-08-17

    申请号：US755503

    申请日：1991-08-27

    申请人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

    发明人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

    IPC分类号： G06F7/575 ,  G06F9/32 ,  G06F9/355 ,  G06F9/38 ,  G06F13/28 ,  G06F15/78

    CPC分类号： G06F7/575 ,  G06F13/28 ,  G06F15/7832 ,  G06F15/7842 ,  G06F15/786 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/355 ,  G06F9/3877 ,  G06F9/3885 ,  G06F2207/3884

    摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

    摘要翻译： 一种简单的电路配置的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。 数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线， 地址产生单元，其能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元 执行阶段

    Digital signal processor having duplex working registers for switching to standby state during interrupt processing
    6.
    发明授权
    Digital signal processor having duplex working registers for switching to standby state during interrupt processing 失效
    具有双工工作寄存器的数字信号处理器，用于在中断处理期间切换到待机状态

    公开(公告)号：US5222241A

    公开(公告)日：1993-06-22

    申请号：US750408

    申请日：1991-08-27

    申请人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

    发明人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

    IPC分类号： G06F7/575 ,  G06F9/32 ,  G06F9/355 ,  G06F9/38 ,  G06F13/28 ,  G06F15/78

    CPC分类号： G06F7/575 ,  G06F13/28 ,  G06F15/7832 ,  G06F15/7842 ,  G06F15/786 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/355 ,  G06F9/3877 ,  G06F9/3885 ,  G06F2207/3884

    摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

    摘要翻译： 一种简单的电路配置的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。 数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线， 地址产生单元，其能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元 执行阶段

    Digital signal processor with conditional branch decision unit and storage of conditional branch decision results
    7.
    发明授权
    Digital signal processor with conditional branch decision unit and storage of conditional branch decision results 失效
    具有条件分支决策单元的数字信号处理器和条件分支决策结果的存储

    公开(公告)号：US5247627A

    公开(公告)日：1993-09-21

    申请号：US750478

    申请日：1991-08-27

    申请人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

    发明人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

    IPC分类号： G06F7/575 ,  G06F9/32 ,  G06F9/355 ,  G06F9/38 ,  G06F13/28 ,  G06F15/78

    CPC分类号： G06F7/575 ,  G06F13/28 ,  G06F15/7832 ,  G06F15/7842 ,  G06F15/786 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/355 ,  G06F9/3877 ,  G06F9/3885 ,  G06F2207/3884

    摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

    摘要翻译： 一种简单的电路配置的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。 数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线， 地址产生单元，其能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元 执行阶段

    Digital signal processor with multiway branching based on parallel evaluation of N threshold values followed by sequential evaluation of M
    9.
    发明授权
    Digital signal processor with multiway branching based on parallel evaluation of N threshold values followed by sequential evaluation of M 失效
    基于并行评估N个阈值的多路分支数字信号处理器，随后对M进行顺序评估

    公开(公告)号：US5388236A

    公开(公告)日：1995-02-07

    申请号：US140989

    申请日：1993-10-25

    申请人： Tokumichi Murakami ,  Naoto Kinjo

    发明人： Tokumichi Murakami ,  Naoto Kinjo

    IPC分类号： G06T7/20 ,  H04N5/14 ,  H04N7/26 ,  G06T1/00

    CPC分类号： G06T7/202 ,  G06T7/2013 ,  G06T7/2026 ,  H04N19/43 ,  H04N19/433 ,  H04N19/51 ,  H04N19/533 ,  H04N5/145 ,  G06T2200/28 ,  G06T2207/10016

    摘要： A digital signal processor having a data decision device for selecting an output from one of an arithmetic calculator within a calculating unit, a logical shifter or a multiplier in parallel with the calculating unit. The data decision device simultaneously compares in parallel selected output data with n-threshold values defining (n+1) data regions for determining in which region among the (n+1) data regions the output data exists. The resultant region in which the output data is determined to exist is compared with m region limiting conditions to output either branch address information when coincidence is found to exist or a signal representative of incoincidence when all of the m conditions are incoincident.

    摘要翻译： 一种数字信号处理器，具有数据判定装置，用于从计算单元中的运算计算器之一选择输出，逻辑移位器或与计算单元并联的乘法器。 数据判定装置将并行选择的输出数据与定义（n + 1）个数据区的n个阈值同时进行比较，以确定存在输出数据的（n + 1）个数据区中的哪个区域。 将输出数据确定存在的合成区域与m个区域限制条件进行比较，以便当发现符合时输出分支地址信息，或者当所有m个条件不一致时，表示不一致的信号。

    Digital signal processor with high speed multiplier means for double data input
    10.
    发明授权
    Digital signal processor with high speed multiplier means for double data input 失效
    数字信号处理器具有高速倍增器，用于双重数据输入

    公开(公告)号：US5442799A

    公开(公告)日：1995-08-15

    申请号：US907233

    申请日：1992-07-01

    申请人： Tokumichi Murakami ,  Naoto Kinjo

    发明人： Tokumichi Murakami ,  Naoto Kinjo

    IPC分类号： G06T7/20 ,  H04N5/14 ,  H04N7/26 ,  G06F7/44

    CPC分类号： G06T7/202 ,  G06T7/2013 ,  G06T7/2026 ,  H04N19/43 ,  H04N19/433 ,  H04N19/51 ,  H04N19/533 ,  H04N5/145 ,  G06T2200/28 ,  G06T2207/10016

    摘要： The present invention improves a digital signal processor, more particularly, calculation methods for motion compensation in reduceing a required amount of calculations when an amount of distortion between a last frame block and a current frame block; in processing a direct memory access at a higher efficiency; in processing a subdivided data calculation at a higher speed; in processing a branch instruction occurring in the pipeline process at a higher efficiency; and in processing an interruption occurring in a repeat process operation at greater convenience, and furthermore in reducing a required amount of calculations through minimum distortion searching processes hierarchized.

    摘要翻译： 本发明改进了数字信号处理器，更具体地，涉及当在最后帧块和当前帧块之间的失真量时减少计算所需量的运动补偿的计算方法; 在更高效率地处理直接存储器访问; 在更高速度处理细分数据计算; 在管理过程中以更高的效率处理分支指令; 并且在更加方便的情况下处理在重复处理操作中发生的中断，并且还通过层级化的最小失真搜索处理来减少所需的计算量。