公开(公告)号：US5161247A

公开(公告)日：1992-11-03

申请号：US379274

申请日：1989-07-13

申请人： Tokumichi Murakami ,  Koh Kamizawa ,  Naoto Kinjo ,  Hideo Ohira ,  Takao Wakabayashi

发明人： Tokumichi Murakami ,  Koh Kamizawa ,  Naoto Kinjo ,  Hideo Ohira ,  Takao Wakabayashi

IPC分类号： G06T7/20 ,  H04N5/14 ,  H04N7/26

CPC分类号： G06T7/202 ,  G06T7/2013 ,  G06T7/2026 ,  H04N19/43 ,  H04N19/433 ,  H04N19/51 ,  H04N19/533 ,  H04N5/145 ,  G06T2200/28 ,  G06T2207/10016

摘要： The present invention improves a digital signal processor, more particularly, calculation methods for motion compensation in reducing a required amount of calculations when an amount of distortion between a last frame block and a current frame block; in processing a direct memory access at a higher efficiency; in processing a subdivided data calculation at a higher speed; in processing a branch instruction occurring in the pipeline process at a higher efficiency; and in processing an interruption occurring in a repeat process operation at greater convenience, and furthermore in reducing a required amount of calculations through minimum distortion searching processes hierarchized.

摘要翻译： 本发明改进了数字信号处理器，更具体地，涉及当在最后帧块和当前帧块之间的失真量时减少计算所需量的运动补偿的计算方法; 在更高效率地处理直接存储器访问; 在更高速度处理细分数据计算; 在管理过程中以更高的效率处理分支指令; 并且在更加方便的情况下处理在重复处理操作中发生的中断，并且还通过层级化的最小失真搜索处理来减少所需的计算量。

公开(公告)号：US5130797A

公开(公告)日：1992-07-14

申请号：US483840

申请日：1990-02-23

申请人： Tokumichi Murakami ,  Koh Kamizawa ,  Hideo Ohira ,  Kohji Ogura ,  Naoto Kinjo ,  Takao Wakabayashi

发明人： Tokumichi Murakami ,  Koh Kamizawa ,  Hideo Ohira ,  Kohji Ogura ,  Naoto Kinjo ,  Takao Wakabayashi

IPC分类号： H04N7/26 ,  H04N7/36 ,  H04N7/46

CPC分类号： H04N19/00 ,  H04N19/43 ,  H04N19/436 ,  H04N19/51 ,  H04N19/533 ,  H04N19/577 ,  H04N19/587 ,  H04N19/30

摘要： A video codec system inputs consecutively frame after frame of sub-sampled video data obtained by sub-sampling video data in units of frames. The video data is coded in parallel by internal coding circuits. This averages the numbers of significant pixels in the sub-sampled video data to be processed. The coded video data is composed so as to comply with specifications of the receiving equipment. Upon transmission, the data is again sub-sampled depending on the number of coding circuits on the receiving side. Each piece of the sub-sampled data is given a header for consecutive transmission. This allows for a certain period of time between pieces of data that arrive at the receiving side, thereby eliminating time differences in receiving and coding.

摘要翻译： 视频编解码器系统以帧为单位对视频数据进行子采样而获得的子采样视频数据的帧后连续输入。 视频数据由内部编码电路并行编码。 这将对待处理的子采样视频数据中的有效像素数进行平均。 编码视频数据被构成为符合接收设备的规格。 在发送时，根据接收侧的编码电路的数量再次对数据进行子采样。 给每个子采样数据提供连续传输的报头。 这允许在到达接收侧的数据段之间的一定时间段，从而消除接收和编码中的时间差异。

公开(公告)号：US5206940A

公开(公告)日：1993-04-27

申请号：US750512

申请日：1991-08-27

申请人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

发明人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

IPC分类号： G06F7/575 ,  G06F9/32 ,  G06F9/355 ,  G06F9/38 ,  G06F13/28 ,  G06F15/78

CPC分类号： G06F7/575 ,  G06F13/28 ,  G06F15/7832 ,  G06F15/7842 ,  G06F15/786 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/355 ,  G06F9/3877 ,  G06F9/3885 ,  G06F2207/3884

摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

摘要翻译： 一种简单的电路配置的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。 数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线， 地址产生单元，其能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元 执行阶段

公开(公告)号：US5237667A

公开(公告)日：1993-08-17

申请号：US755503

申请日：1991-08-27

申请人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

发明人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

IPC分类号： G06F7/575 ,  G06F9/32 ,  G06F9/355 ,  G06F9/38 ,  G06F13/28 ,  G06F15/78

CPC分类号： G06F7/575 ,  G06F13/28 ,  G06F15/7832 ,  G06F15/7842 ,  G06F15/786 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/355 ,  G06F9/3877 ,  G06F9/3885 ,  G06F2207/3884

摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

摘要翻译： 一种简单的电路配置的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。 数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线， 地址产生单元，其能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元 执行阶段

公开(公告)号：US5045993A

公开(公告)日：1991-09-03

申请号：US201208

申请日：1988-06-03

申请人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

发明人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

IPC分类号： G06F7/575 ,  G06F9/32 ,  G06F9/345 ,  G06F9/355 ,  G06F9/38 ,  G06F13/28 ,  G06F15/78

CPC分类号： G06F7/575 ,  G06F13/28 ,  G06F15/7832 ,  G06F15/786 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/345 ,  G06F9/355 ,  G06F9/3877 ,  G06F9/3885 ,  G06F2207/3884

摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

公开(公告)号：US5247627A

公开(公告)日：1993-09-21

申请号：US750478

申请日：1991-08-27

申请人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

发明人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

IPC分类号： G06F7/575 ,  G06F9/32 ,  G06F9/355 ,  G06F9/38 ,  G06F13/28 ,  G06F15/78

CPC分类号： G06F7/575 ,  G06F13/28 ,  G06F15/7832 ,  G06F15/7842 ,  G06F15/786 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/355 ,  G06F9/3877 ,  G06F9/3885 ,  G06F2207/3884

摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

摘要翻译： 一种简单的电路配置的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。 数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线， 地址产生单元，其能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元 执行阶段

公开(公告)号：US5222241A

公开(公告)日：1993-06-22

申请号：US750408

申请日：1991-08-27

申请人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

发明人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

IPC分类号： G06F7/575 ,  G06F9/32 ,  G06F9/355 ,  G06F9/38 ,  G06F13/28 ,  G06F15/78

CPC分类号： G06F7/575 ,  G06F13/28 ,  G06F15/7832 ,  G06F15/7842 ,  G06F15/786 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/355 ,  G06F9/3877 ,  G06F9/3885 ,  G06F2207/3884

摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

摘要翻译： 一种简单的电路配置的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。 数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线， 地址产生单元，其能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元 执行阶段

公开(公告)号：US5504916A

公开(公告)日：1996-04-02

申请号：US128257

申请日：1993-09-28

申请人： Tokumichi Murakami ,  Koh Kamizawa ,  Hideo Ohira

发明人： Tokumichi Murakami ,  Koh Kamizawa ,  Hideo Ohira

IPC分类号： G06T7/20 ,  H04N5/14 ,  H04N7/26 ,  G06F13/32

CPC分类号： G06T7/202 ,  G06T7/2013 ,  G06T7/2026 ,  H04N19/43 ,  H04N19/433 ,  H04N19/51 ,  H04N19/533 ,  H04N5/145 ,  G06T2200/28 ,  G06T2207/10016

摘要： A digital signal processor having a DMA controller adapted for image processing while transmitting data between an internal memory and an external memory. The DMA controller includes a frame horizontal size register for representing a horizontal size of a two dimensional address space and block horizontal size register for representing a horizontal size of a rectangular portion in the two dimensional address space with a block address register for indicating a head address of source area, an internal memory start address register for representing a head address of destination area, and a word register. An address calculation unit in the DMA controller generates addresses based on two horizontal size register. An external data memory connecting unit in DSP for connecting the internal memory and the external memory has two modes. One is a mode of outputting an address in two machine cycles, and the other is a mode of outputting an address in one machine cycle.

摘要翻译： 一种具有DMA控制器的数字信号处理器，适于在内部存储器和外部存储器之间传输数据的同时进行图像处理。 DMA控制器包括用于表示二维地址空间的水平尺寸的帧水平尺寸寄存器和用于表示二维地址空间中的矩形部分的水平尺寸的块水平尺寸寄存器，其具有用于指示头地址的块地址寄存器 的源区域，用于表示目的地区域的头地址的内部存储器起始地址寄存器和字寄存器。 DMA控制器中的地址计算单元基于两个水平尺寸寄存器生成地址。 用于连接内部存储器和外部存储器的DSP中的外部数据存储器连接单元具有两种模式。 一种是在两个机器周期中输出地址的模式，另一种是在一个机器周期中输出地址的模式。

公开(公告)号：US06208689B1

公开(公告)日：2001-03-27

申请号：US08806668

申请日：1997-02-26

申请人： Hideo Ohira ,  Kenichi Asano ,  Toshiaki Shimada ,  Kohtaro Asai ,  Tokumichi Murakami

发明人： Hideo Ohira ,  Kenichi Asano ,  Toshiaki Shimada ,  Kohtaro Asai ,  Tokumichi Murakami

IPC分类号： H04B166

CPC分类号： H04N19/577 ,  H04N19/115 ,  H04N19/126 ,  H04N19/14 ,  H04N19/15 ,  H04N19/159 ,  H04N19/172 ,  H04N19/177 ,  H04N19/423 ,  H04N19/428 ,  H04N19/61

摘要： A method and apparatus of digital image decoding is provided for reducing compression-related deterioration of an image to a minimum with a reduced storage capacity. The digital image decoding apparatus is equipped with a compression rate judging section for judging an optimal rate of compression for effecting the least deterioration to the image based upon the size of image in connection with the storage capacity of a frame memory. A compressing section compresses decoded data based upon the optimal rate of compression and sends the compressed data to a predictive/display frame memory for storage. An expanding A section expands the compressed data based upon the optimal rate of compression and sends the expanded data to a decoding section when the expanded data is required. An expanding B section reads out the compressed data of a display frame from the predictive/display frame memory and expands the compressed data based upon the optimal rate of compression and sends the expanded data to a display unit for display.

摘要翻译： 提供一种数字图像解码的方法和装置，用于以降低的存储容量将图像的压缩相关劣化降至最低。 数字图像解码装置配备有压缩率判定部，其根据与帧存储器的存储容量相关联的图像的大小来判断压缩的最佳速率，以实现图像的劣化。 压缩部分基于最佳压缩率压缩解码数据，并将压缩数据发送到预测/显示帧存储器以进行存储。 扩展的A部分根据最佳压缩速率扩展压缩数据，并在扩展数据需要时将扩展数据发送到解码部分。 扩展B部分从预测/显示帧存储器中读出显示帧的压缩数据，并根据最佳压缩率扩展压缩数据，并将扩展数据发送到显示单元进行显示。

公开(公告)号：US5701159A

公开(公告)日：1997-12-23

申请号：US715161

申请日：1996-09-17

申请人： Hideo Ohira ,  Tokumichi Murakami ,  Kohtaro Asai ,  Toshiaki Shimada

发明人： Hideo Ohira ,  Tokumichi Murakami ,  Kohtaro Asai ,  Toshiaki Shimada

IPC分类号： H04N19/60 ,  G06T9/00 ,  H04N19/115 ,  H04N19/134 ,  H04N19/176 ,  H04N19/423 ,  H04N19/426 ,  H04N19/44 ,  H04N19/503 ,  H04N19/593 ,  H04N19/61 ,  H04N19/625 ,  H04N19/91 ,  H04N7/50

CPC分类号： H04N19/428 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61

摘要： Data which has been decoded by a decoding portion 101 are compressed by a compressing portion 102 and stored in a prediction/display frame memory portion 103. From the data stored in the prediction/display frame memory portion 103, any data required for decoding other frames in the decoding portion 101 are decompressed through a decompressing A portion 104 and supplied to the decoding portion 101. Alternatively, data to be displayed is read from the prediction/display frame memory portion 103, decompressed at a decompressing B portion 105 and supplied to a display apparatus. Writing to and reading from the above-mentioned prediction/display frame memory portion 103 is controlled by an address controlling portion 106. Since compressed data are stored in the prediction/display frame memory portion 103, the memory capacity can be decreased.

摘要翻译： 由解码部分101解码的数据被压缩部分102压缩并存储在预测/显示帧存储器部分103中。从预测/显示帧存储器部分103中存储的数据中，解码其它帧所需的任何数据 在解码部分101中通过解压缩A部分104解压缩并提供给解码部分101.或者，从预测/显示帧存储部分103读取要显示的数据，在解压缩B部分105解压缩并提供给 显示装置。 由地址控制部分106控制对上述预测/显示帧存储器部分103的写入和读取。由于压缩数据被存储在预测/显示帧存储器部分103中，所以可以减小存储器容量。