公开(公告)号：US20210375684A1

公开(公告)日：2021-12-02

申请号：US17329153

申请日：2021-05-25

申请人： Tokyo Electron Limited

发明人： Shimpei YAMAGUCHI ,  Atsushi TSUBOI ,  Atsushi ENDO ,  Masaru SUGIMOTO ,  Hiroshi YANO ,  Yasushi KODASHIMA ,  Masanobu IGETA

IPC分类号： H01L21/8234 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66

摘要： A method for manufacturing a semiconductor device includes forming a support on a side surface of a stack that extends from a substrate. The stack includes a second sacrificial film, plural first sacrificial films and plural silicon (Si)-containing films, wherein one first sacrificial film of the plural sacrificial films is stacked upon the second sacrificial film and the plural sacrificial films and the plural Si-containing films are alternately stacked upon one another, and at least a side of the second sacrificial film is not covered by the support, the one first sacrificial film and the substrate. The method further includes removing the second sacrificial film from the stack to form a space between the substrate and the one first sacrificial film and adjacent to the support, and filling the space with a dielectric film.

公开(公告)号：US20230051865A1

公开(公告)日：2023-02-16

申请号：US17975619

申请日：2022-10-28

申请人： Tokyo Electron Limited

发明人： Takuya SEINO ,  Yasushi KODASHIMA ,  Naoki WATANABE ,  Hiroyuki TOSHIMA ,  Masato SHINADA ,  Tetsuya MIYASHITA

IPC分类号： C23C14/56 ,  C23C14/50

摘要： The PVD apparatus includes a chamber, a plurality of stages, a first target holder, a power supply mechanism, and a shield. The plurality of stages are provided inside the chamber, and each of the plurality of stages is configured to place at least one substrate on an upper surface thereof. The first target holder is configured to hold at least one target provided for one stage, the target being exposed to a space inside the chamber. The power supply mechanism supplies power to the target via the first target holder. The shield is provided inside the chamber and a part of the shield is disposed between a first stage and a second stage in the plurality of stages, and between a first processing space on the first stage and a second processing space on the second stage.