公开(公告)号：US20210280419A1

公开(公告)日：2021-09-09

申请号：US17190818

申请日：2021-03-03

Applicant: Tokyo Electron Limited

Inventor： Noriaki OKABE ,  Takuya SEINO ,  Ryota KOZUKA ,  Yasuhiro HAMADA ,  Yuutaro KISHI

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/308

Abstract: A method of processing a wafer includes preparing a wafer having a substrate and a silicon-containing film formed on the substrate; forming a hard mask on the silicon-containing film; forming a pattern on the hard mask by etching the hard mask; and etching the silicon-containing film using the hard mask on which the pattern is formed, wherein the hard mask has a first film formed on the silicon-containing film and containing tungsten, and a second film formed on the first film and containing zirconium or titanium and oxygen.

公开(公告)号：US20250044704A1

公开(公告)日：2025-02-06

申请号：US18921159

申请日：2024-10-21

Applicant: Tokyo Electron Limited

Inventor： Yuichi ASAHI ,  Takuya SEINO

IPC: G03F7/00 ,  G03F7/16 ,  G03F7/20 ,  H01L21/67

Abstract: A substrate processing method includes: (A) applying a resist liquid on a substrate to form a resist film, (B) performing auxiliary exposure processing of irradiating the resist film with light having a desired wavelength, separately from exposure processing of transferring a pattern of a mask onto the resist film, (C) supplying a developer to the resist film after the exposure processing and the auxiliary exposure processing to form a resist pattern, (D) etching an etching target layer on the substrate using the resist pattern as a mask, and (E) correcting an in-plane distribution of an exposure amount in the auxiliary exposure processing in (B), and performing the correction based on a result of (D) when (A) to (D) are performed under conditions before the correction.

公开(公告)号：US20230178378A1

公开(公告)日：2023-06-08

申请号：US18098112

申请日：2023-01-18

Applicant: Tokyo Electron Limited

Inventor： Noriaki OKABE ,  Naoki SHINDO ,  Gen YOU ,  Takuya SEINO

IPC: H01L21/311 ,  H01L21/67

CPC classification number: H01L21/31116 ,  H01L21/31144 ,  H01L21/67069

Abstract: An etching method includes a preparing step and a removing step. In the preparing step, a substrate is prepared which includes a first film, a second film stacked on the first film, and a hard mask stacked on the second film, such that the second film is etched with the hard mask having a formed pattern as a mask until the first film is exposed. In the removing step, the hard mask is removed using a fluorine-containing gas. Further, the removing step is executed for a time longer than a first time from a start of a supply of the fluorine-containing gas to a start of an etching of the hard mask, and shorter than a second time from the start of the supply of the fluorine-containing gas to a start of an etching of the first film.

公开(公告)号：US20230051865A1

公开(公告)日：2023-02-16

申请号：US17975619

申请日：2022-10-28

Applicant: Tokyo Electron Limited

Inventor： Takuya SEINO ,  Yasushi KODASHIMA ,  Naoki WATANABE ,  Hiroyuki TOSHIMA ,  Masato SHINADA ,  Tetsuya MIYASHITA

IPC: C23C14/56 ,  C23C14/50

Abstract: The PVD apparatus includes a chamber, a plurality of stages, a first target holder, a power supply mechanism, and a shield. The plurality of stages are provided inside the chamber, and each of the plurality of stages is configured to place at least one substrate on an upper surface thereof. The first target holder is configured to hold at least one target provided for one stage, the target being exposed to a space inside the chamber. The power supply mechanism supplies power to the target via the first target holder. The shield is provided inside the chamber and a part of the shield is disposed between a first stage and a second stage in the plurality of stages, and between a first processing space on the first stage and a second processing space on the second stage.