System and method for a floating-point format for digital signal processors

    公开(公告)号:US09792087B2

    公开(公告)日:2017-10-17

    申请号:US13452701

    申请日:2012-04-20

    IPC分类号: G06F7/483

    CPC分类号: G06F7/483

    摘要: An embodiment of a system and method for performing a numerical operation on input data in a hybrid floating-point format includes representing input data as a sign bit, exponent bits, and mantissa bits. The exponent bits are represented as an unsigned integer including an exponent bias, and a signed numerical value of zero is represented as a first reserved combination of the mantissa bits and the exponent bits. Each of all other combinations of the mantissa bits and the exponent bits represents a real finite non-zero number. The mantissa bits are operated on with a “one” bit before a radix point for the all other combinations of the mantissa bits and the exponent bits.

    System and method for signal processing in digital signal processors
    8.
    发明授权
    System and method for signal processing in digital signal processors 有权
    数字信号处理器信号处理系统和方法

    公开(公告)号:US09274750B2

    公开(公告)日:2016-03-01

    申请号:US13452690

    申请日:2012-04-20

    IPC分类号: G06F7/48 G06F7/483 G06F7/544

    摘要: An embodiment of a method and a related apparatus for digital computation of a floating point complex multiply-add is provided. The method includes receiving an input addend, a first product, and a second product. The input addend, the first product and the second product each respectively has a mantissa and an exponent. The method includes shifting the mantissas of the two with smaller exponents of the input addend, the first product, and the second product to align together with the mantissa of the one with largest exponent of the input addend, the first product and the second product, and adding the aligned input addend, the aligned first product and the aligned second product.

    摘要翻译: 提供了一种用于浮点复数乘法的数字计算的方法和相关装置的实施例。 该方法包括接收输入加数,第一产品和第二产品。 输入加法,第一产品和第二产品分别具有尾数和指数。 该方法包括以输入加数,第一乘积和第二乘积的较小指数移动两者的尾数,使其与输入加法器,第一乘积和第二乘积的最大指数的尾数对齐, 并添加对齐的输入加数,对齐的第一个产品和对齐的第二个产品。

    System and Method for Signal Processing in Digital Signal Processors
    10.
    发明申请
    System and Method for Signal Processing in Digital Signal Processors 有权
    数字信号处理器信号处理系统与方法

    公开(公告)号:US20130282778A1

    公开(公告)日:2013-10-24

    申请号:US13452690

    申请日:2012-04-20

    摘要: An embodiment of a method and a related apparatus for digital computation of a floating point complex multiply-add is provided. The method includes receiving an input addend, a first product, and a second product. The input addend, the first product and the second product each respectively has a mantissa and an exponent. The method includes shifting the mantissas of the two with smaller exponents of the input addend, the first product, and the second product to align together with the mantissa of the one with largest exponent of the input addend, the first product and the second product, and adding the aligned input addend, the aligned first product and the aligned second product.

    摘要翻译: 提供了一种用于浮点复数乘法的数字计算的方法和相关装置的实施例。 该方法包括接收输入加数,第一产品和第二产品。 输入加法,第一产品和第二产品分别具有尾数和指数。 该方法包括以输入加数,第一乘积和第二乘积的较小指数移动两者的尾数,使其与输入加法器,第一乘积和第二乘积的最大指数的尾数对齐, 并添加对齐的输入加数,对齐的第一个产品和对齐的第二个产品。