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公开(公告)号：US20080253181A1
公开(公告)日：2008-10-16
申请号：US12061105
申请日：2008-04-02
CPC分类号： G11C16/3418 , G11C16/3427
摘要： A method for programming a semiconductor memory device including such a program sequence as to program target threshold levels constituting multi-level data into multiple memory cells, which are simultaneously selected, wherein the program sequence is controlled to finish programming the multiple memory cells in order of height of the target threshold levels.
摘要翻译： 一种编程半导体存储器件的方法，该半导体存储器件包括这样的程序序列，将构成多级数据的程序目标阈值水平同时选择为多个存储器单元，其中控制该程序序列以完成对多个存储器单元的编程， 目标阈值水平的高度。
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公开(公告)号：US07764542B2
公开(公告)日：2010-07-27
申请号：US12061105
申请日：2008-04-02
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427
摘要： A method for programming a semiconductor memory device including such a program sequence as to program target threshold levels constituting multi-level data into multiple memory cells, which are simultaneously selected, wherein the program sequence is controlled to finish programming the multiple memory cells in order of height of the target threshold levels.
摘要翻译： 一种用于将包括这样的程序序列的半导体存储器件编程的方法，所述程序序列用于将构成多级数据的程序目标阈值水平同时选择为多个存储器单元，其中控制程序序列以完成多个存储器单元的编程， 目标阈值水平的高度。
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公开(公告)号：US08711635B2
公开(公告)日：2014-04-29
申请号：US13618537
申请日：2012-09-14
申请人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
发明人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
IPC分类号： G11C11/34
CPC分类号： G11C16/3454 , G11C16/0483
摘要： A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.
摘要翻译： 非易失性半导体存储器件包括：存储单元，其存储数据并且能够被电气重写;电位地连接到存储单元的电流路径的一端的位线;控制电路，其执行验证操作 在将数据写入存储单元之后检查写入结果;以及电压设置电路，其在验证操作和读取操作中设置位线的充电电压，并使读取操作中的充电电压高于充电电压 验证操作。
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公开(公告)号：US20130010541A1
公开(公告)日：2013-01-10
申请号：US13618537
申请日：2012-09-14
申请人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
发明人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
IPC分类号： G11C16/06
CPC分类号： G11C16/3454 , G11C16/0483
摘要： A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.
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公开(公告)号：US08000155B2
公开(公告)日：2011-08-16
申请号：US13005582
申请日：2011-01-13
申请人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.
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公开(公告)号：US07889537B2
公开(公告)日：2011-02-15
申请号：US12118064
申请日：2008-05-09
申请人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.
摘要翻译： 本发明提供一种将数据写入非易失性存储器件的方法，该非易失性存储器件具有彼此相交的第一布线和第二布线以及布置在其间的每个交叉处的存储单元，每个存储单元具有可变电阻元件和整流元件 系列。 根据该方法，在所选择的第一布线中升高之前，将第二布线充电至不小于整流元件阈值的一定电压。 然后，将所选择的第一布线充电到写入或擦除所需的电压，之后放电所选择的第二布线。
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公开(公告)号：US08315104B2
公开(公告)日：2012-11-20
申请号：US12491638
申请日：2009-06-25
申请人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
发明人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
IPC分类号： G11C11/34
CPC分类号： G11C16/3454 , G11C16/0483
摘要： A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.
摘要翻译： 非易失性半导体存储器件包括：存储单元，其存储数据并且能够被电气重写;电位地连接到存储单元的电流路径的一端的位线;控制电路，其执行验证操作 在将数据写入存储单元之后检查写入结果;以及电压设置电路，其在验证操作和读取操作中设置位线的充电电压，并使读取操作中的充电电压高于充电电压 验证操作。
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公开(公告)号：US20110103135A1
公开(公告)日：2011-05-05
申请号：US13005582
申请日：2011-01-13
申请人： Toshiaki EDAHIRO , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki EDAHIRO , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.
摘要翻译： 本发明提供一种将数据写入非易失性存储器件的方法，该非易失性存储器件具有彼此相交的第一布线和第二布线以及布置在其间的每个交叉处的存储单元，每个存储单元具有可变电阻元件和整流元件 系列。 根据该方法，在所选择的第一布线中升高之前，将第二布线充电至不小于整流元件阈值的一定电压。 然后，将所选择的第一布线充电到写入或擦除所需的电压，之后放电所选择的第二布线。
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公开(公告)号：US20090323432A1
公开(公告)日：2009-12-31
申请号：US12491638
申请日：2009-06-25
申请人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
发明人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
CPC分类号： G11C16/3454 , G11C16/0483
摘要： A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.
摘要翻译： 非易失性半导体存储器件包括：存储单元，其存储数据并且能够被电气重写;电位地连接到存储单元的电流路径的一端的位线;控制电路，其执行验证操作 在将数据写入存储单元之后检查写入结果;以及电压设置电路，其在验证操作和读取操作中设置位线的充电电压，并使读取操作中的充电电压高于充电电压 验证操作。
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公开(公告)号：US20090010039A1
公开(公告)日：2009-01-08
申请号：US12132972
申请日：2008-06-04
申请人： Naoya Tokiwa , Kazushige Kanda , Toshiaki Edahiro , Koji Hosono , Takuya Futatsuyama , Shigeo Ohsima
发明人： Naoya Tokiwa , Kazushige Kanda , Toshiaki Edahiro , Koji Hosono , Takuya Futatsuyama , Shigeo Ohsima
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0097 , G11C2013/0092 , G11C2213/32 , G11C2213/72
摘要： According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; and a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation.
摘要翻译： 根据一个实施例，非易失性存储器件包括：存储单元阵列，其包括各自具有用于非易失性地存储由电可重写电阻值识别的数据的可变电阻元件的存储单元; 存储要写入存储单元阵列的给定组的存储单元的用于写入和擦除操作的写入和擦除数据的第一数据锁存器; 以及第二数据锁存器，存储用于执行给定组的补偿操作以补偿伴随着写入或擦除操作的写入和擦除干扰的参考数据。
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