公开(公告)号：US08004446B2

公开(公告)日：2011-08-23

申请号：US12529092

申请日：2008-02-28

申请人： Toshiaki Ozeki ,  Koji Oka ,  Daisuke Nomasaki ,  Ikuo Hidaka ,  Yoshikazu Makabe

发明人： Toshiaki Ozeki ,  Koji Oka ,  Daisuke Nomasaki ,  Ikuo Hidaka ,  Yoshikazu Makabe

IPC分类号： H03M1/38

CPC分类号： H03M1/1215 ,  H03M1/168

摘要： An A/D converter which converts an analog input signal into a digital output signal by performing time-divisional parallel processings on the analog input signal using first and second pipeline type unit A/D converters. The A/D converter sets plural unit A/D converters performing parallel processings according to a system request, such that, when the A/D converter operates with a conversion frequency that is lower than the maximum conversion frequency, the unit A/D converter is halted by a control signal, thereby reducing inter-channel errors among the unit A/D converters to improve the precision of the A/D converter.

摘要翻译： A / D转换器，其通过使用第一和第二流水线型单元A / D转换器对模拟输入信号执行时分并行处理，将模拟输入信号转换为数字输出信号。 A / D转换器根据系统请求设置多个单元A / D转换器，执行并行处理，使得当A / D转换器以低于最大转换频率的转换频率工作时，单元A / D转换器 被控制信号停止，从而减少单元A / D转换器之间的通道间误差，以提高A / D转换器的精度。

公开(公告)号：US20100117879A1

公开(公告)日：2010-05-13

申请号：US12529092

申请日：2008-02-28

申请人： Toshiaki Ozeki ,  Koji Oka ,  Daisuke Nomasaki ,  Ikuo Hidaka ,  Yoshikazu Makabe

发明人： Toshiaki Ozeki ,  Koji Oka ,  Daisuke Nomasaki ,  Ikuo Hidaka ,  Yoshikazu Makabe

IPC分类号： H03M1/00 ,  H03M1/12 ,  H03M1/36

CPC分类号： H03M1/1215 ,  H03M1/168

摘要： An A/D converter which converts an analog input signal into a digital output signal by performing time-divisional parallel processings on the analog input signal using first and second pipeline type unit A/D converters (121,122), has a function of setting plural unit A/D converters which perform parallel processings according to a system request, and when the A/D converter is operated with a conversion frequency that is lower than the maximum conversion frequency, the unit A/D converter (122) is halted by a control signal (15), thereby reducing inter-channel errors among the unit A/D converters to improve the precision of the A/D converter.

摘要翻译： 通过使用第一和第二流水线型单元A / D转换器（121,122）对模拟输入信号进行时分并行处理，将模拟输入信号转换为数字输出信号的A / D转换器具有设定多个单元 A / D转换器，其根据系统请求执行并行处理，当A / D转换器以低于最大转换频率的转换频率工作时，单元A / D转换器（122）通过控制 信号（15），从而减少单元A / D转换器之间的通道间误差，提高A / D转换器的精度。

公开(公告)号：US20080158035A1

公开(公告)日：2008-07-03

申请号：US11964943

申请日：2007-12-27

申请人： Yoshikazu Makabe ,  Ikuo Hidaka ,  Koji Oka ,  Toshiaki Ozeki

发明人： Yoshikazu Makabe ,  Ikuo Hidaka ,  Koji Oka ,  Toshiaki Ozeki

IPC分类号： H03M1/12 ,  G06F1/04 ,  H03K3/356

CPC分类号： H03M1/0624 ,  G06F1/06 ,  H03K5/151 ,  H03M1/1215

摘要： A first Delayed Flip Flop includes a first D input terminal, a first clock input terminal, a first output terminal outputting a signal inputted to the first D input terminal based on the clock signal, and a first inversion output terminal inverting and outputting the signal inputted to the first D input terminal and outputting the signal to the first D input terminal as a feedback. A second Delayed Flip Flop includes a second D input terminal receiving the output from the first output terminal of the first Delayed Flip Flop, a second clock input terminal, and a second output terminal outputting the signal inputted to the second D input terminal as a first output based on the clock signal. A third Delayed Flip Flop includes a third D input terminal receiving the output from the first inversion output terminal of the first Delayed Flip Flop, a third clock input terminal, and a third output terminal outputting the signal inputted to the third D input terminal as a second output based on the clock signal. The first output and the second output have signal waveforms inverted at the same timing.

摘要翻译： 第一延迟触发器包括第一D输入端子，第一时钟输入端子，基于时钟信号输出输入到第一D输入端子的信号的第一输出端子和反相输出的第一反相输出端子 到第一D输入端，并将信号输出到第一D输入端作为反馈。 第二延迟触发器包括第二D输入端子，其接收来自第一延迟触发器的第一输出端子的输出，第二时钟输入端子和第二输出端子，该第二输出端子输入输入到第二D输入端子的信号作为第一延迟触发器 基于时钟信号输出。 第三延迟触发器包括接收第一延迟触发器的第一反相输出端子的输出的第三D输入端子，第三时钟输入端子以及输入到第三D输入端子的信号的第三输出端子，作为 基于时钟信号的第二输出。 第一输出和第二输出具有在相同定时反转的信号波形。

公开(公告)号：US07609194B2

公开(公告)日：2009-10-27

申请号：US11964943

申请日：2007-12-27

申请人： Yoshikazu Makabe ,  Ikuo Hidaka ,  Koji Oka ,  Toshiaki Ozeki

发明人： Yoshikazu Makabe ,  Ikuo Hidaka ,  Koji Oka ,  Toshiaki Ozeki

IPC分类号： H03M1/12

CPC分类号： H03M1/0624 ,  G06F1/06 ,  H03K5/151 ,  H03M1/1215

摘要： A first Delayed Flip Flop includes a first D input terminal, a first clock input terminal, a first output terminal outputting a signal inputted to the first D input terminal based on the clock signal, and a first inversion output terminal inverting and outputting the signal inputted to the first D input terminal and outputting the signal to the first D input terminal as a feedback. A second Delayed Flip Flop includes a second D input terminal receiving the output from the first output terminal of the first Delayed Flip Flop, a second clock input terminal, and a second output terminal outputting the signal inputted to the second D input terminal as a first output based on the clock signal. A third Delayed Flip Flop includes a third D input terminal receiving the output from the first inversion output terminal of the first Delayed Flip Flop, a third clock input terminal, and a third output terminal outputting the signal inputted to the third D input terminal as a second output based on the clock signal. The first output and the second output have signal waveforms inverted at the same timing.

摘要翻译： 第一延迟触发器包括第一D输入端子，第一时钟输入端子，基于时钟信号输出输入到第一D输入端子的信号的第一输出端子和反相输出的第一反相输出端子 到第一D输入端，并将信号输出到第一D输入端作为反馈。 第二延迟触发器包括第二D输入端子，其接收来自第一延迟触发器的第一输出端子的输出，第二时钟输入端子和第二输出端子，该第二输出端子输入输入到第二D输入端子的信号作为第一延迟触发器 基于时钟信号输出。 第三延迟触发器包括接收第一延迟触发器的第一反相输出端子的输出的第三D输入端子，第三时钟输入端子以及输入到第三D输入端子的信号的第三输出端子，作为 基于时钟信号的第二输出。 第一输出和第二输出具有在相同定时反转的信号波形。

公开(公告)号：US06339579B1

公开(公告)日：2002-01-15

申请号：US09287338

申请日：1999-04-07

申请人： Yuichi Kamioka ,  Kenji Koishi ,  Yoshiyuki Miyabata ,  Naoyuki Nakamura ,  Kenichi Tatehara ,  Ikuo Hidaka ,  Kiyoshi Nakamori

发明人： Yuichi Kamioka ,  Kenji Koishi ,  Yoshiyuki Miyabata ,  Naoyuki Nakamura ,  Kenichi Tatehara ,  Ikuo Hidaka ,  Kiyoshi Nakamori

IPC分类号： G11B700

CPC分类号： G11B7/126 ,  H01S5/042 ,  H01S5/0683 ,  H01S5/0687

摘要： In an optical disc apparatus, a semiconductor SLD driving device is mounted on an optical pickup in order to realize a high speed switching of drive current for a semiconductor laser diode (SLD), necessary for recording data. The SLD is placed. within 5 cm from the SLD driving device. The driving device becomes a heat source due to driving current of the SLD, and increases a temperature of the optical pickup. Since the temperature rises proportionally to power consumption, power saving is required. A voltage supplied to the driving device is controlled to be a minimum level necessary for keeping the driving device still working on basic functions. The SLD driving device is mounted to the optical pickup, and this driving device handles N pieces of input signals for setting semiconductor laser power and N pieces of switch-timing-input-signals for selecting respective input signals. A supplied voltage is controlled so that a voltage supplied to the output section of the driving device is a minimum value necessary for keeping the output section still operating. A power source is placed outside of the pickup.

摘要翻译： 在光盘装置中，半导体SLD驱动装置安装在光学拾取器上，以实现用于记录数据所需的用于半导体激光二极管（SLD）的驱动电流的高速切换。 放置SLD。 距离SLD驱动装置5厘米以内。 驱动装置由于SLD的驱动电流而成为热源，并且提高了光学拾取器的温度。 由于温度与功耗成比例上升，因此需要省电。 被提供给驱动装置的电压被控制为使驱动装置保持基本功能所必需的最低水平。 SLD驱动装置安装在光拾取器上，该驱动装置处理N条输入信号以设置半导体激光功率，并且N条开关定时输入信号用于选择各个输入信号。 控制供电电压，使得提供给驱动装置的输出部分的电压是保持输出部分仍然工作所需的最小值。 电源放置在拾音器外面。