公开(公告)号：US08004446B2

公开(公告)日：2011-08-23

申请号：US12529092

申请日：2008-02-28

申请人： Toshiaki Ozeki ,  Koji Oka ,  Daisuke Nomasaki ,  Ikuo Hidaka ,  Yoshikazu Makabe

发明人： Toshiaki Ozeki ,  Koji Oka ,  Daisuke Nomasaki ,  Ikuo Hidaka ,  Yoshikazu Makabe

IPC分类号： H03M1/38

CPC分类号： H03M1/1215 ,  H03M1/168

摘要： An A/D converter which converts an analog input signal into a digital output signal by performing time-divisional parallel processings on the analog input signal using first and second pipeline type unit A/D converters. The A/D converter sets plural unit A/D converters performing parallel processings according to a system request, such that, when the A/D converter operates with a conversion frequency that is lower than the maximum conversion frequency, the unit A/D converter is halted by a control signal, thereby reducing inter-channel errors among the unit A/D converters to improve the precision of the A/D converter.

摘要翻译： A / D转换器，其通过使用第一和第二流水线型单元A / D转换器对模拟输入信号执行时分并行处理，将模拟输入信号转换为数字输出信号。 A / D转换器根据系统请求设置多个单元A / D转换器，执行并行处理，使得当A / D转换器以低于最大转换频率的转换频率工作时，单元A / D转换器 被控制信号停止，从而减少单元A / D转换器之间的通道间误差，以提高A / D转换器的精度。

公开(公告)号：US20080158035A1

公开(公告)日：2008-07-03

申请号：US11964943

申请日：2007-12-27

申请人： Yoshikazu Makabe ,  Ikuo Hidaka ,  Koji Oka ,  Toshiaki Ozeki

发明人： Yoshikazu Makabe ,  Ikuo Hidaka ,  Koji Oka ,  Toshiaki Ozeki

IPC分类号： H03M1/12 ,  G06F1/04 ,  H03K3/356

CPC分类号： H03M1/0624 ,  G06F1/06 ,  H03K5/151 ,  H03M1/1215

摘要： A first Delayed Flip Flop includes a first D input terminal, a first clock input terminal, a first output terminal outputting a signal inputted to the first D input terminal based on the clock signal, and a first inversion output terminal inverting and outputting the signal inputted to the first D input terminal and outputting the signal to the first D input terminal as a feedback. A second Delayed Flip Flop includes a second D input terminal receiving the output from the first output terminal of the first Delayed Flip Flop, a second clock input terminal, and a second output terminal outputting the signal inputted to the second D input terminal as a first output based on the clock signal. A third Delayed Flip Flop includes a third D input terminal receiving the output from the first inversion output terminal of the first Delayed Flip Flop, a third clock input terminal, and a third output terminal outputting the signal inputted to the third D input terminal as a second output based on the clock signal. The first output and the second output have signal waveforms inverted at the same timing.

摘要翻译： 第一延迟触发器包括第一D输入端子，第一时钟输入端子，基于时钟信号输出输入到第一D输入端子的信号的第一输出端子和反相输出的第一反相输出端子 到第一D输入端，并将信号输出到第一D输入端作为反馈。 第二延迟触发器包括第二D输入端子，其接收来自第一延迟触发器的第一输出端子的输出，第二时钟输入端子和第二输出端子，该第二输出端子输入输入到第二D输入端子的信号作为第一延迟触发器 基于时钟信号输出。 第三延迟触发器包括接收第一延迟触发器的第一反相输出端子的输出的第三D输入端子，第三时钟输入端子以及输入到第三D输入端子的信号的第三输出端子，作为 基于时钟信号的第二输出。 第一输出和第二输出具有在相同定时反转的信号波形。

公开(公告)号：US20120170773A1

公开(公告)日：2012-07-05

申请号：US13141293

申请日：2010-09-07

申请人： Yoshikazu Makabe ,  Shuya Yamasaki

发明人： Yoshikazu Makabe ,  Shuya Yamasaki

IPC分类号： H03F1/26 ,  H03F99/00

CPC分类号： H03F1/26 ,  H03F1/52 ,  H03F1/523 ,  H03F3/185 ,  H03F2200/444

摘要： An amplifier 100 with a high-frequency noise removing function according to the present invention includes: an input terminal 101 to which an input signal is input; a ground terminal 102 maintained at a reference potential; a resistor 111 connected to the input terminal; an amplifying circuit 201 configured to amplify and output the input signal input through the resistor; and an output terminal 103 through which an output signal output from the amplifying circuit is output. The amplifying circuit includes a parasitic capacitance 112 configured to be connected to between one terminal of the resistor, the terminal being located on the opposite side of the input terminal, and the ground terminal, and the resistor and the parasitic capacitance constitute a low-pass filter 113.

摘要翻译： 根据本发明的具有高频噪声消除功能的放大器100包括：输入信号被输入的输入端101; 接地端子102保持在参考电位; 连接到输入端子的电阻器111; 被配置为放大并输出通过电阻器输入的输入信号的放大电路201; 以及从放大电路输出的输出信号输出的输出端子103。 放大电路包括：寄生电容112，被配置为连接到电阻器的一个端子之间，端子位于输入端子的相对侧，接地端子，电阻器和寄生电容构成低通 过滤器113。

公开(公告)号：US20100117879A1

公开(公告)日：2010-05-13

申请号：US12529092

申请日：2008-02-28

申请人： Toshiaki Ozeki ,  Koji Oka ,  Daisuke Nomasaki ,  Ikuo Hidaka ,  Yoshikazu Makabe

发明人： Toshiaki Ozeki ,  Koji Oka ,  Daisuke Nomasaki ,  Ikuo Hidaka ,  Yoshikazu Makabe

IPC分类号： H03M1/00 ,  H03M1/12 ,  H03M1/36

CPC分类号： H03M1/1215 ,  H03M1/168

摘要： An A/D converter which converts an analog input signal into a digital output signal by performing time-divisional parallel processings on the analog input signal using first and second pipeline type unit A/D converters (121,122), has a function of setting plural unit A/D converters which perform parallel processings according to a system request, and when the A/D converter is operated with a conversion frequency that is lower than the maximum conversion frequency, the unit A/D converter (122) is halted by a control signal (15), thereby reducing inter-channel errors among the unit A/D converters to improve the precision of the A/D converter.

摘要翻译： 通过使用第一和第二流水线型单元A / D转换器（121,122）对模拟输入信号进行时分并行处理，将模拟输入信号转换为数字输出信号的A / D转换器具有设定多个单元 A / D转换器，其根据系统请求执行并行处理，当A / D转换器以低于最大转换频率的转换频率工作时，单元A / D转换器（122）通过控制 信号（15），从而减少单元A / D转换器之间的通道间误差，提高A / D转换器的精度。

公开(公告)号：US20070146955A1

公开(公告)日：2007-06-28

申请号：US11645767

申请日：2006-12-27

申请人： Yoshikazu Makabe ,  Makoto Yamamoto

发明人： Yoshikazu Makabe ,  Makoto Yamamoto

IPC分类号： H02H9/06

CPC分类号： H01L27/0259 ,  H01L2924/0002 ,  H03F1/52 ,  H03F2200/258 ,  H03F2200/441 ,  H03F2200/444 ,  H01L2924/00

摘要： A semiconductor integrated circuit device has an internal circuit connected to each of an external terminal, a high-potential power source terminal, and a low-potential power source terminal, a surge protection circuit connected between the external terminal and the low-potential power source terminal to protect the internal circuit from a surge voltage applied to the external terminal, a capacitor having one terminal connected to the external terminal, a transistor connected between the other terminal of the capacitor and the low-potential power source terminal, and a control circuit which brings the internal circuit into a stopped state and does not activate the transistor when the surge voltage is applied to the external terminal.

摘要翻译： 半导体集成电路器件具有连接到外部端子，高电位电源端子和低电位电源端子的内部电路，连接在外部端子和低电位电源之间的浪涌保护电路 端子，用于保护内部电路免受施加到外部端子的浪涌电压，具有连接到外部端子的一个端子的电容器，连接在电容器的另一端子与低电位电源端子之间的晶体管和控制电路 这使得内部电路处于停止状态，并且当浪涌电压施加到外部端子时不激活晶体管。

公开(公告)号：US07609194B2

公开(公告)日：2009-10-27

申请号：US11964943

申请日：2007-12-27

申请人： Yoshikazu Makabe ,  Ikuo Hidaka ,  Koji Oka ,  Toshiaki Ozeki

发明人： Yoshikazu Makabe ,  Ikuo Hidaka ,  Koji Oka ,  Toshiaki Ozeki

IPC分类号： H03M1/12

CPC分类号： H03M1/0624 ,  G06F1/06 ,  H03K5/151 ,  H03M1/1215

摘要： A first Delayed Flip Flop includes a first D input terminal, a first clock input terminal, a first output terminal outputting a signal inputted to the first D input terminal based on the clock signal, and a first inversion output terminal inverting and outputting the signal inputted to the first D input terminal and outputting the signal to the first D input terminal as a feedback. A second Delayed Flip Flop includes a second D input terminal receiving the output from the first output terminal of the first Delayed Flip Flop, a second clock input terminal, and a second output terminal outputting the signal inputted to the second D input terminal as a first output based on the clock signal. A third Delayed Flip Flop includes a third D input terminal receiving the output from the first inversion output terminal of the first Delayed Flip Flop, a third clock input terminal, and a third output terminal outputting the signal inputted to the third D input terminal as a second output based on the clock signal. The first output and the second output have signal waveforms inverted at the same timing.

摘要翻译： 第一延迟触发器包括第一D输入端子，第一时钟输入端子，基于时钟信号输出输入到第一D输入端子的信号的第一输出端子和反相输出的第一反相输出端子 到第一D输入端，并将信号输出到第一D输入端作为反馈。 第二延迟触发器包括第二D输入端子，其接收来自第一延迟触发器的第一输出端子的输出，第二时钟输入端子和第二输出端子，该第二输出端子输入输入到第二D输入端子的信号作为第一延迟触发器 基于时钟信号输出。 第三延迟触发器包括接收第一延迟触发器的第一反相输出端子的输出的第三D输入端子，第三时钟输入端子以及输入到第三D输入端子的信号的第三输出端子，作为 基于时钟信号的第二输出。 第一输出和第二输出具有在相同定时反转的信号波形。