公开(公告)号：US07884750B2

公开(公告)日：2011-02-08

申请号：US12643613

申请日：2009-12-21

申请人： Toshiaki Ozeki ,  Daisuke Nomasaki ,  Koji Oka

发明人： Toshiaki Ozeki ,  Daisuke Nomasaki ,  Koji Oka

IPC分类号： H03M1/38

CPC分类号： H03M1/168

摘要： In an A/D converter provided with an A/D converter circuit 101 for operationally amplifying an input signal and outputting an amplified signal, the A/D converter circuit 101 includes an initial value setting circuit 4a in addition to an amplifier 1a, a sub-A/D converter 2a, a sub-D/A converter 3a and capacitors C11 and C12. To ensure that the initial value of the output voltage of the amplifier 1a is a given voltage value close to the target value of operational amplification at the start of the operational amplification by the amplifier 1a, the initial value setting circuit 4a applies a given bias value equal to the given voltage value close to the target value to a next-stage capacitor C13 to be connected to the output side of the amplifier 1a. Such an A/D converter circuit 101 that can perform speedy convergence to the target value of operational amplification is used at each stage of a pipeline A/D converter.

摘要翻译： A / D变换电路101具备A / D转换电路101，用于对输入信号进行运算放大并输出放大信号，A / D变换电路101除了具有放大器1a以外还包括初始值设定电路4a A / D转换器2a，子D / A转换器3a和电容器C11和C12。 为了确保放大器1a的输出电压的初始值为放大器1a在工作放大开始时接近于工作放大的目标值的给定电压值，初始值设定电路4a施加给定的偏置值 等于接近目标值的给定电压值连接到放大器1a的输出侧的下一级电容器C13。 在流水线A / D转换器的各阶段使用能够对运算放大的目标值进行快速收敛的A / D转换电路101。

公开(公告)号：US20090040088A1

公开(公告)日：2009-02-12

申请号：US11631844

申请日：2006-03-24

申请人： Toshiaki Ozeki ,  Daisuke Nomasaki ,  Koji Oka

发明人： Toshiaki Ozeki ,  Daisuke Nomasaki ,  Koji Oka

IPC分类号： H03M1/38

CPC分类号： H03M1/168

摘要： In an A/D converter provided with an A/D converter circuit 101 for operationally amplifying an input signal and outputting an amplified signal, the A/D converter circuit 101 includes an initial value setting circuit 4a in addition to an amplifier 1a, a sub-A/D converter 2a, a sub-D/A converter 3a and capacitors C11 and C12. To ensure that the initial value of the output voltage of the amplifier 1a is a given voltage value close to the target value of operational amplification at the start of the operational amplification by the amplifier 1a, the initial value setting circuit 4a applies a given bias value equal to the given voltage value close to the target value to a next-stage capacitor C13 to be connected to the output side of the amplifier 1a. Such an A/D converter circuit 101 that can perform speedy convergence to the target value of operational amplification is used at each stage of a pipeline A/D converter.

摘要翻译： A / D变换电路101具备A / D转换电路101，用于对输入信号进行运算放大并输出放大信号，A / D变换电路101除了具有放大器1a以外还包括初始值设定电路4a A / D转换器2a，子D / A转换器3a和电容器C11和C12。 为了确保放大器1a的输出电压的初始值为放大器1a在工作放大开始时接近于工作放大的目标值的给定电压值，初始值设定电路4a施加给定的偏置值 等于接近目标值的给定电压值连接到放大器1a的输出侧的下一级电容器C13。 在流水线A / D转换器的各阶段使用能够对运算放大的目标值进行快速收敛的A / D转换电路101。

公开(公告)号：US20110298642A1

公开(公告)日：2011-12-08

申请号：US13210863

申请日：2011-08-16

申请人： Daisuke NOMASAKI ,  Takeshi OKUMOTO

发明人： Daisuke NOMASAKI ,  Takeshi OKUMOTO

IPC分类号： H03M1/10 ,  H03K17/687

CPC分类号： H03F3/345 ,  G05F3/26 ,  H03F2200/252 ,  H03F2200/417 ,  H03F2203/45136 ,  H03F2203/45646 ,  H03M1/1019 ,  H03M1/44

摘要： A current is generated from a reference voltage using an operational amplifier. The current is mirrored by a current mirror circuit to obtain a reference current. For example, the current mirror circuit includes a plurality of PMOS transistors. Based on the result of measurement of the reference current by an external monitor, the connection destination of the gate voltage of each of a plurality of mirror destination current source transistors is switched by an analog switch circuit between a power supply and the gate of a mirror source current source transistor, thereby changing the number of mirror destination current source transistors which are turned on, to change a current minor ratio. Thus, the current can be trimmed.

摘要翻译： 使用运算放大器从参考电压产生电流。 电流由电流镜电路镜像，以获得参考电流。 例如，电流镜电路包括多个PMOS晶体管。 基于由外部监视器测量参考电流的结果，多个镜像目的电流源晶体管中的每一个的栅极电压的连接目的地由电源和镜的栅极之间的模拟开关电路切换 源电流源晶体管，从而改变导通的镜像目的电流源晶体管的数量，以改变当前较小的比率。 因此，可以修剪电流。

公开(公告)号：US20110254125A1

公开(公告)日：2011-10-20

申请号：US12600094

申请日：2008-05-16

申请人： Daisuke Nomasaki ,  Koji Oka ,  Toshiaki Ozeki

发明人： Daisuke Nomasaki ,  Koji Oka ,  Toshiaki Ozeki

IPC分类号： H01L27/00

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L2224/05553 ,  H01L2224/06 ,  H01L2924/0002 ,  H03H11/04 ,  H03H2001/0014 ,  H03L7/0891 ,  H03L7/093 ,  H01L2924/00

摘要： A semiconductor integrated circuit according to the present invention is equipped with a plurality of analog macros having comb capacitors (10), each comb capacitor (10) has a comb-shaped first electrode (11) and a comb-shaped second electrode (12), comb tooth portions (13) of the electrode (11) and comb tooth portions (14) of the electrode (12) are engaged so that the comb tooth portions (13) and the comb tooth portions (14) are arranged alternately and parallel to one another, and a comb tooth interval S of the comb capacitor is varied according to an absolute accuracy indicating an error between an actual capacitance value and an ideal capacitance value, or a relative accuracy indicating a difference in capacitance values between adjacent comb capacitors. Thereby, it is possible to provide a semiconductor integrated circuit which is equipped with highly-accurate analog macros and highly-integrated analog macros having comb capacitors which ensure high capacitance accuracies.

摘要翻译： 根据本发明的半导体集成电路配备有具有梳状电容器（10）的多个模拟宏，每个梳状电容器（10）具有梳状的第一电极（11）和梳状的第二电极（12） 电极（11）的梳齿部（13）和电极（12）的梳齿部（14）接合，使得梳齿部（13）和梳齿部（14）交替平行配置 并且梳状电容器的梳齿间隔S根据指示实际电容值和理想电容值之间的误差的绝对精度或指示相邻梳状电容器之间的电容值差的相对精度而变化。 因此，可以提供一种半导体集成电路，其配备有高精度模拟宏和具有确保高电容精度的梳状电容器的高度集成的模拟宏。

公开(公告)号：US06734817B2

公开(公告)日：2004-05-11

申请号：US10328159

申请日：2002-12-26

申请人： Junichi Naka ,  Yoshitsugu Inagaki ,  Hiroshi Sakura ,  Heiji Ikoma ,  Koji Oka ,  Youichi Okamoto ,  Daisuke Nomasaki

发明人： Junichi Naka ,  Yoshitsugu Inagaki ,  Hiroshi Sakura ,  Heiji Ikoma ,  Koji Oka ,  Youichi Okamoto ,  Daisuke Nomasaki

IPC分类号： H03M112

CPC分类号： H03M1/002 ,  H03M1/007 ,  H03M1/12

摘要： When the performance of an A/D converter required by a system changes, power consumption of the overall system can be reduced. The resolution of an A/D converter is made variable by changing a current flowing through an amplifier by an external control signal that specifies the resolution. Thus, when the performance required by a system changes, it is possible to change the performance of the A/D converter and to prevent a performance overhead of the A/D converter. Consequently, power consumption of the A/D converter is reduced, and power consumption of the system as a whole is also reduced.

摘要翻译： 当系统所需的A / D转换器的性能改变时，可以降低整个系统的功耗。 通过用指定分辨率的外部控制信号改变流过放大器的电流，可以使A / D转换器的分辨率可变。 因此，当系统所需的性能改变时，可以改变A / D转换器的性能并且防止A / D转换器的性能开销。 因此，A / D转换器的功耗降低，整个系统的功耗也降低。

公开(公告)号：US20100270648A1

公开(公告)日：2010-10-28

申请号：US12829760

申请日：2010-07-02

申请人： Yoshinori MIYADA ,  Kenji MURATA ,  Daisuke NOMASAKI

发明人： Yoshinori MIYADA ,  Kenji MURATA ,  Daisuke NOMASAKI

IPC分类号： H01L27/06

CPC分类号： H01L27/0805 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.

摘要翻译： 半导体集成电路具有多个电容器单元，并且每个电容器单元具有上电极和下电极。 这些电极分别连接到上电极布线和下电极。 当例如上电极连接到上电极布线并且电极布线位于另一个电容器单元的下电极的一侧或连接这些电极的下电极布线的一侧时，屏蔽布线设置在 上电极布线和另一个电容器单元的相邻位置的下电极或上电极布线和相邻位置的下电极布线之间。 因此，利用该屏蔽布线，可以有效地抑制电容器单元的各布线与电容器单元的每个上电极或每个下电极之间的电容耦合。

公开(公告)号：US20100188151A1

公开(公告)日：2010-07-29

申请号：US12445003

申请日：2008-07-30

申请人： Daisuke Nomasaki ,  Koji Oka

发明人： Daisuke Nomasaki ,  Koji Oka

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H01L27/0629 ,  H01L27/0811 ,  H01L27/088 ,  H03F2203/45352 ,  H03F2203/45371 ,  H03F2203/45486 ,  H03M1/0682 ,  H03M1/0695 ,  H03M1/442

摘要： A differential voltage interconnect (W101a) electrically connects the gate electrode of a transistor to be used among differential transistors (T101a, T101a, . . . ) to an input node receiving an input voltage (Vinn), and a differential voltage interconnect (W101b) electrically connects the gate electrode of a transistor to be used among differential transistors (T101b, T101b, . . . ) to an input node receiving an input voltage (Vinp). A bias voltage interconnect (W102) electrically connects the gate electrode of a transistor to be used among current source transistors (T102, T102, . . . ) to a bias node receiving a bias voltage (VBN), and a bias voltage interconnect (W103) electrically connects the gate electrodes of transistors to be used among load transistors (T103a, T103a, T103b, T103b, . . . ) to a bias node receiving a bias voltage (VBP).

摘要翻译： 差分电压互连（W101a）将要用于差分晶体管（T101a，T101a ...等）的晶体管的栅极电连接到接收输入电压（Vinn）的输入节点和差分电压互连（W101b） 将待使用的晶体管的栅电极（T101b，T101b ...）电连接到接收输入电压（Vinp）的输入节点。 偏置电压互连（W102）将要用于电流源晶体管（T102，T102 ......）中的晶体管的栅极电连接到接收偏置电压（VBN）的偏置节点和偏置电压互连（W103 ）将负载晶体管（T103a，T103a，T103b，T103b ...等）中使用的晶体管的栅极电连接到接收偏置电压（VBP）的偏置节点。

公开(公告)号：US20100117879A1

公开(公告)日：2010-05-13

申请号：US12529092

申请日：2008-02-28

申请人： Toshiaki Ozeki ,  Koji Oka ,  Daisuke Nomasaki ,  Ikuo Hidaka ,  Yoshikazu Makabe

发明人： Toshiaki Ozeki ,  Koji Oka ,  Daisuke Nomasaki ,  Ikuo Hidaka ,  Yoshikazu Makabe

IPC分类号： H03M1/00 ,  H03M1/12 ,  H03M1/36

CPC分类号： H03M1/1215 ,  H03M1/168

摘要： An A/D converter which converts an analog input signal into a digital output signal by performing time-divisional parallel processings on the analog input signal using first and second pipeline type unit A/D converters (121,122), has a function of setting plural unit A/D converters which perform parallel processings according to a system request, and when the A/D converter is operated with a conversion frequency that is lower than the maximum conversion frequency, the unit A/D converter (122) is halted by a control signal (15), thereby reducing inter-channel errors among the unit A/D converters to improve the precision of the A/D converter.

摘要翻译： 通过使用第一和第二流水线型单元A / D转换器（121,122）对模拟输入信号进行时分并行处理，将模拟输入信号转换为数字输出信号的A / D转换器具有设定多个单元 A / D转换器，其根据系统请求执行并行处理，当A / D转换器以低于最大转换频率的转换频率工作时，单元A / D转换器（122）通过控制 信号（15），从而减少单元A / D转换器之间的通道间误差，提高A / D转换器的精度。

公开(公告)号：US07649487B2

公开(公告)日：2010-01-19

申请号：US11631844

申请日：2006-03-24

申请人： Toshiaki Ozeki ,  Daisuke Nomasaki ,  Koji Oka

发明人： Toshiaki Ozeki ,  Daisuke Nomasaki ,  Koji Oka

IPC分类号： H03M1/38

CPC分类号： H03M1/168

摘要： In an A/D converter provided with an A/D converter circuit 101 for operationally amplifying an input signal and outputting an amplified signal, the A/D converter circuit 101 includes an initial value setting circuit 4a in addition to an amplifier 1a, a sub-A/D converter 2a, a sub-D/A converter 3a and capacitors C11 and C12. To ensure that the initial value of the output voltage of the amplifier 1a is a given voltage value close to the target value of operational amplification at the start of the operational amplification by the amplifier 1a, the initial value setting circuit 4a applies a given bias value equal to the given voltage value close to the target value to a next-stage capacitor C13 to be connected to the output side of the amplifier 1a. Such an A/D converter circuit 101 that can perform speedy convergence to the target value of operational amplification is used at each stage of a pipeline A/D converter.

摘要翻译： A / D变换电路101具备A / D转换电路101，用于对输入信号进行运算放大并输出放大信号，A / D变换电路101除了具有放大器1a以外还包括初始值设定电路4a A / D转换器2a，子D / A转换器3a和电容器C11和C12。 为了确保放大器1a的输出电压的初始值为放大器1a在工作放大开始时接近于工作放大的目标值的给定电压值，初始值设定电路4a施加给定的偏置值 等于接近目标值的给定电压值连接到放大器1a的输出侧的下一级电容器C13。 在流水线A / D转换器的各阶段使用能够对运算放大的目标值进行快速收敛的A / D转换电路101。

公开(公告)号：US08004446B2

公开(公告)日：2011-08-23

申请号：US12529092

申请日：2008-02-28

申请人： Toshiaki Ozeki ,  Koji Oka ,  Daisuke Nomasaki ,  Ikuo Hidaka ,  Yoshikazu Makabe

发明人： Toshiaki Ozeki ,  Koji Oka ,  Daisuke Nomasaki ,  Ikuo Hidaka ,  Yoshikazu Makabe

IPC分类号： H03M1/38

CPC分类号： H03M1/1215 ,  H03M1/168

摘要： An A/D converter which converts an analog input signal into a digital output signal by performing time-divisional parallel processings on the analog input signal using first and second pipeline type unit A/D converters. The A/D converter sets plural unit A/D converters performing parallel processings according to a system request, such that, when the A/D converter operates with a conversion frequency that is lower than the maximum conversion frequency, the unit A/D converter is halted by a control signal, thereby reducing inter-channel errors among the unit A/D converters to improve the precision of the A/D converter.

摘要翻译： A / D转换器，其通过使用第一和第二流水线型单元A / D转换器对模拟输入信号执行时分并行处理，将模拟输入信号转换为数字输出信号。 A / D转换器根据系统请求设置多个单元A / D转换器，执行并行处理，使得当A / D转换器以低于最大转换频率的转换频率工作时，单元A / D转换器 被控制信号停止，从而减少单元A / D转换器之间的通道间误差，以提高A / D转换器的精度。