公开(公告)号：US09804795B2

公开(公告)日：2017-10-31

申请号：US15061216

申请日：2016-03-04

Applicant: Toshiba Memory Corporation

Inventor： Yoon Tze Chin ,  Norikazu Yoshida ,  Mitsuru Anazawa

IPC: G11C5/14 ,  G06F3/06 ,  G11C16/30 ,  G11C11/4074

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0679 ,  G06F13/16 ,  G11C5/14 ,  G11C5/143 ,  G11C5/147 ,  G11C7/04 ,  G11C11/4074 ,  G11C16/30 ,  Y02D10/154

Abstract: A memory including non-volatile memory. The memory system also includes a controller that controls data transfer between a host and the non-volatile memory, and a power supply unit that supplies a voltage to the controller. Further, the controller includes a power supply control unit that determines the voltage supplied to a module in the controller on the basis of an operation condition determined with the host. The power supply unit adjusts the voltage supplied to the module in accordance with a command from the power supply control unit.

公开(公告)号：US10061527B2

公开(公告)日：2018-08-28

申请号：US15714710

申请日：2017-09-25

Applicant: Toshiba Memory Corporation

Inventor： Yoon Tze Chin ,  Norikazu Yoshida ,  Mitsuru Anazawa

IPC: G11C5/14 ,  G06F3/06 ,  G11C11/4074 ,  G11C16/30

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0679 ,  G06F13/16 ,  G11C5/14 ,  G11C5/143 ,  G11C5/147 ,  G11C7/04 ,  G11C11/4074 ,  G11C16/30 ,  Y02D10/154

Abstract: A memory system includes non-volatile memory. The memory system includes a controller that controls data transfer between a host and the non-volatile memory, and a power supply unit that supplies a voltage to the controller. Further, the controller includes a power supply control unit that determines the voltage supplied to a module in the controller on the basis of an operation condition determined with the host. The power supply unit adjusts the voltage supplied to the module in accordance with a command from the power supply control unit.

公开(公告)号：US11036659B2

公开(公告)日：2021-06-15

申请号：US16557371

申请日：2019-08-30

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoon Tze Chin

IPC: G06F13/18 ,  G06F13/42 ,  G06F13/16

Abstract: According to one embodiment, a memory system includes a nonvolatile memory (NVM) and a controller. The controller communicates with an external device via virtual channels (VC) defined in PCI Express Base Specification (PCIe). The external device communicates with the NVM of the memory system per NVM Express Base Specification (NVMe). The controller manages a set of priority relation information (PRI), which maps each priority of Weighted Round Robin with Urgent Priority Class Arbitration mechanism defined in NVMe, to a specific VC. Using the PRI, the controller ensures that the same VC is used throughout the command execution transactions. Quality of Service of communication between the external device and the memory system can thus be improved.