公开(公告)号：US11073896B2

公开(公告)日：2021-07-27

申请号：US16174959

申请日：2018-10-30

Applicant: Toshiba Memory Corporation

Inventor： Mitsuru Anazawa ,  Norikazu Yoshida ,  Takashi Yamaguchi

IPC: G06F1/32 ,  G06F1/28 ,  G06F1/3287 ,  G06F3/06

Abstract: A storage device comprises a nonvolatile memory, a controller that controls access to the nonvolatile memory, and a power circuit that supplies power to the nonvolatile memory and the controller. The power circuit can control the supply of power to at least parts of the nonvolatile memory and at least parts of the controller. The controller executes a data save process when a sleep transition request is received from the host requesting at least one of a plurality of sleep states according to a requested sleep state of the sleep transition request. The controller provides the host with state transition determination information that includes at one of a power consumption amount for a transition to a sleep state from an idle state and power consumption amount for a transition from the sleep state to the idle state.

公开(公告)号：US10331552B2

公开(公告)日：2019-06-25

申请号：US14833280

申请日：2015-08-24

Applicant: Toshiba Memory Corporation

Inventor： Isao Konuma ,  Norikazu Yoshida

IPC: G06F12/00 ,  G06F12/02

Abstract: According to one embodiment, a storage device includes a storage portion storing a first entry, the first entry includes a first translation table corresponding between a first logical address and a first physical address on a nonvolatile memory, and a first state showing that data at the first physical address is a valid as data at the first logical address, and a controller adding a second entry in the storage portion and changing the first state to a second state when receiving a command from a host, the second entry includes a second translation table corresponding between a second logical address and the first physical address, and a third state showing that the first physical address of the second translation table is referring to the first physical address of the first translation table, the second state showing that the first physical address of the first translation table is shared with the first physical address of the second translation table.

公开(公告)号：US09804795B2

公开(公告)日：2017-10-31

申请号：US15061216

申请日：2016-03-04

Applicant: Toshiba Memory Corporation

Inventor： Yoon Tze Chin ,  Norikazu Yoshida ,  Mitsuru Anazawa

IPC: G11C5/14 ,  G06F3/06 ,  G11C16/30 ,  G11C11/4074

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0679 ,  G06F13/16 ,  G11C5/14 ,  G11C5/143 ,  G11C5/147 ,  G11C7/04 ,  G11C11/4074 ,  G11C16/30 ,  Y02D10/154

Abstract: A memory including non-volatile memory. The memory system also includes a controller that controls data transfer between a host and the non-volatile memory, and a power supply unit that supplies a voltage to the controller. Further, the controller includes a power supply control unit that determines the voltage supplied to a module in the controller on the basis of an operation condition determined with the host. The power supply unit adjusts the voltage supplied to the module in accordance with a command from the power supply control unit.

公开(公告)号：US10289560B2

公开(公告)日：2019-05-14

申请号：US15267718

申请日：2016-09-16

Applicant: Toshiba Memory Corporation

Inventor： Norikazu Yoshida ,  Takashi Yamaguchi

IPC: G06F13/40 ,  G06F12/1009 ,  G06F13/42

Abstract: According to one embodiment, a switch module includes a first port with PCIe/NVMe standard being connectable to a host, second ports with PCIe/NVMe standard being connectable to storage devices respectively, and a controller to make the host recognize the storage devices as a virtual storage device.

公开(公告)号：US10236044B2

公开(公告)日：2019-03-19

申请号：US15693410

申请日：2017-08-31

Applicant: Toshiba Memory Corporation

Inventor： Norikazu Yoshida

IPC: G11C8/16 ,  G11C16/08 ,  G06F12/02

Abstract: A memory system includes a semiconductor memory and a controller. The controller is configured to perform a read operation on the semiconductor memory in response to a read instruction received from a host. In response to the read instruction that includes a first logical address, the controller converts the first logical address into a first physical address, and issues a read command and a second physical address different from the first physical address, to the semiconductor memory.

公开(公告)号：US10445018B2

公开(公告)日：2019-10-15

申请号：US15450407

申请日：2017-03-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takashi Yamaguchi ,  Norikazu Yoshida ,  Mitsuru Anazawa

IPC: G06F13/42 ,  G06F3/06 ,  G06F13/40

Abstract: A switch according to an embodiment includes a first PCIe interface that can be connected to a host on the basis of a PCIe standard. In addition, the switch includes a plurality of second PCIe interfaces that can be connected to a plurality of storage devices, respectively, on the basis of the PCIe standard. The switch further includes a control unit that distributes an access request which is comply with an NVMe standard and is transmitted from the host to any one of the plurality of second PCIe interfaces. The distribution includes a process of constructing an NVMe command of the access request and a process of constructing a data transmission descriptor list of the access request.

公开(公告)号：US10061527B2

公开(公告)日：2018-08-28

申请号：US15714710

申请日：2017-09-25

Applicant: Toshiba Memory Corporation

Inventor： Yoon Tze Chin ,  Norikazu Yoshida ,  Mitsuru Anazawa

IPC: G11C5/14 ,  G06F3/06 ,  G11C11/4074 ,  G11C16/30

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0679 ,  G06F13/16 ,  G11C5/14 ,  G11C5/143 ,  G11C5/147 ,  G11C7/04 ,  G11C11/4074 ,  G11C16/30 ,  Y02D10/154

Abstract: A memory system includes non-volatile memory. The memory system includes a controller that controls data transfer between a host and the non-volatile memory, and a power supply unit that supplies a voltage to the controller. Further, the controller includes a power supply control unit that determines the voltage supplied to a module in the controller on the basis of an operation condition determined with the host. The power supply unit adjusts the voltage supplied to the module in accordance with a command from the power supply control unit.