公开(公告)号：US07135773B2

公开(公告)日：2006-11-14

申请号：US10787640

申请日：2004-02-26

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H. Mitchell ,  Stanislav Polonsky

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H. Mitchell ,  Stanislav Polonsky

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： B82Y10/00 ,  H01L21/28562 ,  H01L21/76877 ,  H01L23/5226 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/842 ,  H01L2924/00

摘要： Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.

摘要翻译： 集成电路中的导电路径使用嵌入导电金属中的多个未分化碳纳米管形成，优选为铜。 优选地，导电路径包括在导电层之间运行的通孔。 优选地，通过在通孔位置的导体上形成金属催化剂垫，沉积和蚀刻介电层以形成空腔，在空腔中的催化剂上基本上平行地生长碳纳米管，并填充其中的剩余空隙来形成复合通孔 有铜的腔。 然后在通孔上形成下一导电层。

公开(公告)号：US07473633B2

公开(公告)日：2009-01-06

申请号：US11458726

申请日：2006-07-20

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H Mitchell ,  Stanislav Polonsky

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H Mitchell ,  Stanislav Polonsky

IPC分类号： H01L21/4763

CPC分类号： B82Y10/00 ,  H01L21/28562 ,  H01L21/76877 ,  H01L23/5226 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/842 ,  H01L2924/00

摘要： Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.

摘要翻译： 集成电路中的导电路径使用嵌入导电金属中的多个未分化碳纳米管形成，优选为铜。 优选地，导电路径包括在导电层之间延伸的通孔。 优选地，通过在通孔位置的导体上形成金属催化剂垫，沉积和蚀刻介电层以形成空腔，在空腔中的催化剂上基本上平行地生长碳纳米管，并填充其中的剩余空隙来形成复合通孔 有铜的腔。 然后在通孔上形成下一导电层。

公开(公告)号：US07566613B2

公开(公告)日：2009-07-28

申请号：US11221118

申请日：2005-09-07

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H. Mitchell

IPC分类号： H01L21/8244

CPC分类号： H01L27/108 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785

摘要： A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device.

摘要翻译： 用于存储器电路的存储增益单元，由多个存储器增益单元形成的存储器电路，以及制造这种存储器增益单元和存储器电路的方法。 存储器增益单元包括能够保存存储的电荷的存储装置，写入装置和读取装置。 读取装置包括半导体材料的翅片，鳍片侧面的电隔离的第一和第二栅电极，以及形成在与第一和第二栅电极相邻的鳍片中的源极和漏极。 第一栅电极与存储装置电耦合。 第一和第二栅极电极用于选通限定在源极和漏极之间的鳍片的区域，从而调节从源极流到漏极的电流。 当门控时，电流的大小取决于存储设备存储的电量。

公开(公告)号：US07674674B2

公开(公告)日：2010-03-09

申请号：US12144139

申请日：2008-06-23

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H. Mitchell

IPC分类号： H01L21/8244

CPC分类号： H01L27/108 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785

摘要： A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device.

摘要翻译： 用于存储器电路的存储增益单元，由多个存储器增益单元形成的存储器电路，以及制造这种存储器增益单元和存储器电路的方法。 存储器增益单元包括能够保存存储的电荷的存储装置，写入装置和读取装置。 读取装置包括半导体材料的翅片，鳍片侧面的电隔离的第一和第二栅电极，以及形成在与第一和第二栅电极相邻的鳍片中的源极和漏极。 第一栅电极与存储装置电耦合。 第一和第二栅极电极用于选通限定在源极和漏极之间的鳍片的区域，从而调节从源极流到漏极的电流。 当门控时，电流的大小取决于存储设备存储的电量。

公开(公告)号：US07109546B2

公开(公告)日：2006-09-19

申请号：US10879815

申请日：2004-06-29

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H. Mitchell

IPC分类号： H01L31/119

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C13/0033 ,  G11C2213/17 ,  H01L27/108 ,  H01L27/10861 ,  H01L27/10873 ,  Y10S977/742

摘要： A gain cell for a memory circuit, a memory circuit formed from multiple gain cells, and methods of fabricating such gain cells and memory circuits. The memory gain cell includes a storage capacitor, a write device electrically coupled with the storage capacitor for charging and discharging the storage capacitor to define a stored electrical charge, and a read device. The read device includes one or more semiconducting carbon nanotubes each electrically coupled between a source and drain. A portion of each semiconducting carbon nanotube is gated by the read gate and the storage capacitor to thereby regulate a current flowing through each semiconducting carbon nanotube from the source to the drain. The current is proportional to the electrical charge stored by the storage capacitor. In certain embodiments, the memory gain cell may include multiple storage capacitors.

摘要翻译： 用于存储器电路的增益单元，由多个增益单元形成的存储器电路，以及制造这种增益单元和存储器电路的方法。 存储增益单元包括存储电容器，与存储电容器电耦合以对存储电容器进行充电和放电以定义存储的电荷的写入装置和读取装置。 读取装置包括一个或多个半导体碳纳米管，每个碳纳米管电耦合在源极和漏极之间。 每个半导体碳纳米管的一部分由读取栅极和存储电容器选通，从而调节从源极到漏极流过每个半导体碳纳米管的电流。 电流与存储电容器存储的电荷成比例。 在某些实施例中，存储增益单元可以包括多个存储电容器。

公开(公告)号：US06970372B1

公开(公告)日：2005-11-29

申请号：US10879833

申请日：2004-06-29

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H. Mitchell

IPC分类号： G11C7/00 ,  H01L27/108

CPC分类号： H01L27/108 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785

摘要： A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device.

摘要翻译： 用于存储器电路的存储增益单元，由多个存储器增益单元形成的存储器电路，以及制造这种存储器增益单元和存储器电路的方法。 存储器增益单元包括能够保存存储的电荷的存储装置，写入装置和读取装置。 读取装置包括半导体材料的翅片，鳍片侧面的电隔离的第一和第二栅电极，以及形成在与第一和第二栅电极相邻的鳍片中的源极和漏极。 第一栅电极与存储装置电耦合。 第一和第二栅极电极用于选通限定在源极和漏极之间的鳍片的区域，从而调节从源极流到漏极的电流。 当门控时，电流的大小取决于存储设备存储的电量。

公开(公告)号：US20080261363A1

公开(公告)日：2008-10-23

申请号：US12144139

申请日：2008-06-23

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger ,  Mark Eliot Masters ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger ,  Mark Eliot Masters ,  Peter H. Mitchell

IPC分类号： H01L21/8242

CPC分类号： H01L27/108 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785

摘要： A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device.

摘要翻译： 用于存储器电路的存储增益单元，由多个存储器增益单元形成的存储器电路，以及制造这种存储器增益单元和存储器电路的方法。 存储器增益单元包括能够保存存储的电荷的存储装置，写入装置和读取装置。 读取装置包括半导体材料的翅片，鳍片侧面的电隔离的第一和第二栅电极，以及形成在与第一和第二栅电极相邻的鳍片中的源极和漏极。 第一栅电极与存储装置电耦合。 第一和第二栅极电极用于选通限定在源极和漏极之间的鳍片的区域，从而调节从源极流到漏极的电流。 当门控时，电流的大小取决于存储设备存储的电量。