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公开(公告)号：US20070054503A1
公开(公告)日：2007-03-08
申请号：US11510679
申请日：2006-08-28
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/0228 , C23C16/44 , C23C16/45525 , H01L21/02164 , H01L21/02181 , H01L21/02189 , H01L21/022 , H01L21/28079 , H01L21/28194 , H01L21/3141 , H01L29/495 , H01L29/517
摘要： A method of forming a film on a substrate includes a first step of carrying out first film formation on an insulation layer formed on the substrate by an ALD process, and a second step of carrying out second film formation in continuation to the first step by a CVD process.
摘要翻译： 在衬底上形成膜的方法包括：通过ALD工艺在形成在衬底上的绝缘层上进行第一膜形成的第一步骤;以及第二步骤，通过第一步骤进行第二膜形成 CVD工艺。
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公开(公告)号：US07618855B2
公开(公告)日：2009-11-17
申请号：US11540506
申请日：2006-10-02
IPC分类号： H01L21/8238
CPC分类号： H01L21/823835 , H01L21/28052 , H01L21/28097 , H01L21/28518 , H01L29/4975 , H01L29/6659
摘要： A technology capable of improving the yield in a manufacturing process of a MISFET with a gate electrode formed of a metal silicide film. A gate insulating film is formed on a semiconductor substrate and silicon gate electrodes formed of a polysilicon film are formed on the gate insulating film. Then, after a silicon oxide film is formed so as to cover the silicon gate electrodes, a surface of the silicon oxide film is polished by CMP, thereby exposing the surface of the silicon gate electrodes. Subsequently, a patterned insulating film is formed on the silicon oxide film. Thereafter, an adhesion film is formed on the silicon oxide film and the insulating film. Then, a nickel film is formed on the adhesion film. Thereafter, a silicide reaction is caused to occur between the silicon gate electrode and the nickel film via the adhesion film.
摘要翻译： 一种能够通过由金属硅化物膜形成的栅电极在MISFET的制造工艺中提高产量的技术。 在半导体衬底上形成栅极绝缘膜，在栅极绝缘膜上形成由多晶硅膜形成的硅栅电极。 然后，在形成氧化硅膜以覆盖硅栅电极之后，通过CMP抛光氧化硅膜的表面，从而暴露硅栅电极的表面。 随后，在氧化硅膜上形成图案化的绝缘膜。 此后，在氧化硅膜和绝缘膜上形成粘合膜。 然后，在粘合膜上形成镍膜。 此后，通过粘合膜在硅栅电极和镍膜之间发生硅化物反应。
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3.发明申请公开(公告)号：US20070221970A1
公开(公告)日：2007-09-27
申请号：US11715353
申请日：2007-03-08
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823842 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： In a manufacturing process of a semiconductor device having a CMISFET, first, a silicon film and a first metal film made of a first metal are reacted with each other through heat treatment, thereby forming a gate electrode of a p-channel type MISFET and a dummy gate electrode of an n-channel type MISFET, which are formed of metal silicide. Subsequently, an insulating film is formed so as to cover the gate electrode but expose the dummy electrode, and then, a metal film formed of a second metal having a work function lower than that of the first metal. The metal film contacts with the dummy gate but not with the gate electrode due to the insulating film interposing therebetween. Thereafter, through heat treatment, the dummy gate electrode and the metal film are reacted with each other to form a gate electrode of the n-channel type MISFET.
摘要翻译： 在具有CMISFET的半导体器件的制造工艺中，首先，由第一金属制成的硅膜和第一金属膜通过热处理彼此反应，从而形成p沟道型MISFET的栅电极和 由金属硅化物形成的n沟道型MISFET的虚拟栅电极。 随后，形成绝缘膜以覆盖栅电极，但暴露虚拟电极，然后形成由功函数低于第一金属功函数的第二金属形成的金属膜。 金属膜与虚拟栅极接触，但由于绝缘膜介于其间，与栅电极接触。 此后，通过热处理，虚拟栅电极和金属膜彼此反应，形成n沟道型MISFET的栅电极。
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公开(公告)号：US20070210354A1
公开(公告)日：2007-09-13
申请号：US11713627
申请日：2007-03-05
IPC分类号： H01L29/76
CPC分类号： H01L21/823842 , H01L21/823857 , H01L29/517
摘要： Provided is a technology capable of improving the productivity of a p channel MISFET using a high dielectric-constant film as a gate insulating film and a conductive film containing metal as a gate electrode. In this technology, a threshold voltage of the p channel MISFET can be decreased even if a work function value of the conductive film containing metal at the time of contacting a silicon oxide film is away from a value near a valence band of silicon. A p channel MISFET formed on a semiconductor substrate has a gate insulating film formed of a hafnium oxide film, a metal oxide film formed of an aluminum oxide film on this gate insulating film, and a gate electrode formed of a tantalum nitride film on this metal oxide film. The metal oxide film has a function to shift a work function value of the gate electrode.
摘要翻译： 提供了能够提高使用高介电常数膜作为栅极绝缘膜的p沟道MISFET和含有金属作为栅电极的导电膜的生产率的技术。 在该技术中，即使在接触氧化硅膜时含有金属的导电膜的功函数值远离硅的价带附近的值，也可以降低p沟道MISFET的阈值电压。 形成在半导体基板上的p沟道MISFET具有由氧化铪膜形成的栅极绝缘膜，在该栅极绝缘膜上由氧化铝膜形成的金属氧化物膜，以及在该金属上由氮化钽膜形成的栅电极 氧化膜。 金属氧化物膜具有使栅电极的功函数值偏移的功能。
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公开(公告)号：US20070087537A1
公开(公告)日：2007-04-19
申请号：US11540506
申请日：2006-10-02
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823835 , H01L21/28052 , H01L21/28097 , H01L21/28518 , H01L29/4975 , H01L29/6659
摘要： A technology capable of improving the yield in a manufacturing process of a MISFET with a gate electrode formed of a metal silicide film. A gate insulating film is formed on a semiconductor substrate and silicon gate electrodes formed of a polysilicon film are formed on the gate insulating film. Then, after a silicon oxide film is formed so as to cover the silicon gate electrodes, a surface of the silicon oxide film is polished by CMP, thereby exposing the surface of the silicon gate electrodes. Subsequently, a patterned insulating film is formed on the silicon oxide film. Thereafter, an adhesion film is formed on the silicon oxide film and the insulating film. Then, a nickel film is formed on the adhesion film. Thereafter, a silicide reaction is caused to occur between the silicon gate electrode and the nickel film via the adhesion film.
摘要翻译： 一种能够通过由金属硅化物膜形成的栅电极在MISFET的制造工艺中提高产量的技术。 在半导体衬底上形成栅极绝缘膜，在栅极绝缘膜上形成由多晶硅膜形成的硅栅电极。 然后，在形成氧化硅膜以覆盖硅栅电极之后，通过CMP抛光氧化硅膜的表面，从而暴露硅栅电极的表面。 随后，在氧化硅膜上形成图案化的绝缘膜。 此后，在氧化硅膜和绝缘膜上形成粘合膜。 然后，在粘合膜上形成镍膜。 此后，通过粘合膜在硅栅电极和镍膜之间发生硅化物反应。
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公开(公告)号：US20060214207A1
公开(公告)日：2006-09-28
申请号：US11389121
申请日：2006-03-27
IPC分类号： H01L29/94
CPC分类号： H01L21/823842 , H01L21/823857
摘要： Threshold voltage of a CMOS transistor which uses a gate insulator made of a hafnium-based high-k material is optimized. A gate insulator of nMOS and pMOS transistors includes a HfOx film and a HfAlOx film formed thereon. At this time, silicon atoms in a n type polycrystalline silicon film which constitutes a gate electrode and Hf atoms in the HfAlOx film are bonded (Hf—Si bonding) and silicon atoms in the n type polycrystalline silicon film and Al atoms in the HfAlOx film are bonded (Al—O—Si bonding) at the interface between the HfAlOx film and the gate electrode. Consequently, the work function of the n type polycrystalline silicon and the work function of the p type polycrystalline silicon are controlled so as to be symmetrical with respect to a midgap (threshold voltage of MOS transistor=0) by changing the Al concentration in the HfAlOx film.
摘要翻译： 使用由基于铪的高k材料制成的栅绝缘体的CMOS晶体管的阈值电压被优化。 nMOS和pMOS晶体管的栅极绝缘体包括在其上形成的HfO x膜和HfAlO x膜。 此时，构成栅电极的多晶硅膜中的Hf原子和HfAlOx膜中的Hf原子之间的硅原子（Hf-Si键合）和n型多晶硅膜中的硅原子和HfAlO x膜中的Al原子是 在HfAlOx膜和栅极之间的界面处键合（Al-O-Si键合）。 因此，通过改变HfAlO x中的Al浓度，控制n型多晶硅的功函数和p型多晶硅的功函数相对于中间隙（MOS晶体管= 0的阈值电压）对称 电影。
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公开(公告)号：US20060091474A1
公开(公告)日：2006-05-04
申请号：US11260188
申请日：2005-10-28
IPC分类号： H01L29/76
CPC分类号： H01L21/823842
摘要： The manufacturing process of a semiconductor device in which a n channel MIS transistor and a p channel MIS transistor each having a gate electrode made of a metal material formed on a gate insulator made of a high dielectric constant material are used to form a CMOS circuit is simplified. After simultaneously forming the gate electrodes of the n channel MIS transistor and the p channel MIS transistor by patterning a platinum film deposited on a gate insulator made of a hafnium oxide film, only the gate insulator on the side of the n channel MIS transistor is selectively reduced by using the catalytic reduction of the platinum film. By doing so, the work function of the gate electrode of the n channel MIS transistor is changed.
摘要翻译： 使用其中使用由具有由高介电常数材料制成的栅极绝缘体上形成的由金属材料制成的栅电极的n沟道MIS晶体管和p沟道MIS晶体管形成CMOS电路的半导体器件的制造工艺来形成CMOS电路。 在通过对沉积在由氧化铪膜构成的栅极绝缘体上的铂膜进行图案化而同时形成n沟道MIS晶体管和p沟道MIS晶体管的栅极之后，仅选择性地在n沟道MIS晶体管侧的栅极绝缘体 通过使用铂膜的催化还原来减少。 通过这样做，改变n沟道MIS晶体管的栅电极的功函数。
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公开(公告)号：US07820503B2
公开(公告)日：2010-10-26
申请号：US12219897
申请日：2008-07-30
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28185 , H01L29/6659 , H01L29/7833
摘要： An object of the present invention is to simplify manufacturing process of an n channel MIS transistor and a p channel MIS transistor with gate electrodes formed of a metal material. For its achievement, gate electrodes of each of the n channel MIS transistor and the p channel MIS transistor are simultaneously formed by patterning ruthenium film deposited on a gate insulator. Next, by introducing oxygen into each of the gate electrodes, the gate electrodes are transformed into those having high work function. Thereafter, by selectively reducing the gate electrode of the n channel MIS transistor, it is transformed into a gate electrode having low work function.
摘要翻译： 本发明的一个目的是简化n沟道MIS晶体管和具有由金属材料形成的栅电极的p沟道MIS晶体管的制造工艺。 为了实现，通过图案化沉积在栅极绝缘体上的钌膜，同时形成n沟道MIS晶体管和p沟道MIS晶体管中的每一个的栅电极。 接下来，通过将氧气引入每个栅电极，将栅电极转变为具有高功函数的栅电极。 此后，通过选择性地还原n沟道MIS晶体管的栅电极，将其转换成具有低功函数的栅电极。
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公开(公告)号：US07323381B2
公开(公告)日：2008-01-29
申请号：US11180657
申请日：2005-07-14
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A structure of a MIS transistor for realizing a CMOS circuit capable of simultaneously achieving the high ON current and the low power consumption is provided. Each of the gate insulators of an n channel MIS transistor and a p channel MIS transistor is composed of a hafnium oxide (HfO2) film. Also, the gate electrode of the n channel MIS transistor is composed of an Ni (nickel) silicide film, and the gate electrode of the p channel MIS transistor is composed of a Pt (platinum) film. In this structure, Fermi level pinning of the gate electrodes can be prevented. Therefore, the increase of the threshold voltage of the n channel MIS transistor and the p channel MIS transistor can be inhibited.
摘要翻译： 提供了用于实现能够同时实现高导通电流和低功耗的CMOS电路的MIS晶体管的结构。 n沟道MIS晶体管和p沟道MIS晶体管的每个栅绝缘体由氧化铪（HfO 2 O 2）膜组成。 此外，n沟道MIS晶体管的栅电极由Ni（镍）硅化物膜构成，p沟道MIS晶体管的栅电极由Pt（铂）膜构成。 在这种结构中，可以防止栅电极的费米能级钉扎。 因此，可以抑制n沟道MIS晶体管和p沟道MIS晶体管的阈值电压的增加。
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公开(公告)号：US20070096157A1
公开(公告)日：2007-05-03
申请号：US11515797
申请日：2006-09-06
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L21/823842 , H01L21/28185 , H01L29/6659 , H01L29/7833
摘要： An object of the present invention is to simplify manufacturing process of an n channel MIS transistor and a p channel MIS transistor with gate electrodes formed of a metal material. For its achievement, gate electrodes of each of the n channel MIS transistor and the p channel MIS transistor are simultaneously formed by patterning ruthenium film deposited on a gate insulator. Next, by introducing oxygen into each of the gate electrodes, the gate electrodes are transformed into those having high work function. Thereafter, by selectively reducing the gate electrode of the n channel MIS transistor, it is transformed into a gate electrode having low work function.
摘要翻译： 本发明的一个目的是简化n沟道MIS晶体管和具有由金属材料形成的栅电极的p沟道MIS晶体管的制造工艺。 为了实现，通过图案化沉积在栅极绝缘体上的钌膜，同时形成n沟道MIS晶体管和p沟道MIS晶体管中的每一个的栅电极。 接下来，通过将氧气引入每个栅电极，将栅电极转变为具有高功函数的栅电极。 此后，通过选择性地还原n沟道MIS晶体管的栅电极，将其转换成具有低功函数的栅电极。
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