公开(公告)号：US20110227044A1

公开(公告)日：2011-09-22

申请号：US13046940

申请日：2011-03-14

申请人： Shigeru Kawanaka ,  Kanna Adachi ,  Toshitaka Miyata ,  Hideji Tsujii

发明人： Shigeru Kawanaka ,  Kanna Adachi ,  Toshitaka Miyata ,  Hideji Tsujii

IPC分类号： H01L29/08 ,  B82Y99/00

CPC分类号： H01L29/78684 ,  B82Y10/00 ,  H01L29/1606 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/778 ,  H01L29/7839

摘要： In one embodiment, a transistor includes: a substrate; a source electrode formed on the substrate; a drain electrode formed on the substrate; a graphene film formed between the source electrode and the drain electrode, the graphene film having a semiconductor region including a source side end and a conductor region including a drain side end, a width of the source side end of the graphene film in a channel width direction being narrower than a width of the drain side end of the graphene film in the channel width direction; and a gate electrode formed via a gate insulating film on the semiconductor region of the graphene film and the conductor region of the graphene film. The source electrode is connected to the source side end of the graphene film with a Schottky contact, and the drain electrode is connected to the drain side end of the graphene film with an ohmic contact.

摘要翻译： 在一个实施例中，晶体管包括：衬底; 形成在所述基板上的源电极; 形成在所述基板上的漏电极; 形成在源电极和漏电极之间的石墨烯膜，所述石墨烯膜具有包括源极侧端部和包括漏极侧端部的导体区域的半导体区域，所述石墨烯膜的源极侧端部的宽度在沟道宽度 方向比通道宽度方向上的石墨烯膜的漏极侧端部的宽度窄; 以及在石墨烯膜的半导体区域和石墨烯膜的导体区域上经由栅极绝缘膜形成的栅电极。 源电极以肖特基接触连接到石墨烯膜的源侧端，并且漏电极以欧姆接触连接到石墨烯膜的漏极侧端。

公开(公告)号：US20110220865A1

公开(公告)日：2011-09-15

申请号：US13044727

申请日：2011-03-10

申请人： Toshitaka Miyata ,  Kanna Adachi ,  Shigeru Kawanaka ,  Shu Nakaharai

发明人： Toshitaka Miyata ,  Kanna Adachi ,  Shigeru Kawanaka ,  Shu Nakaharai

IPC分类号： H01L29/66 ,  B82Y99/00

CPC分类号： H01L29/1606 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/0895 ,  H01L29/7391 ,  H01L29/7781 ,  H01L29/7839 ,  H01L29/78684 ,  H01L29/78696 ,  H01L29/872

摘要： According to an embodiment of the present invention, a transistor includes a source electrode, a drain electrode, a graphene film formed between the source electrode and the drain electrode and having a first region and a second region, and a gate electrode formed on the first region and the second region of the graphene film via a gate insulating film. The graphene film functions as a channel. A Schottky junction is formed at a junction between the first region and the second region. The first region has a conductor property, and the second region is adjacent to the drain electrode side of the first region and has a semiconductor property.

摘要翻译： 根据本发明的实施例，晶体管包括源电极，漏电极，形成在源电极和漏电极之间并具有第一区和第二区的石墨烯膜，以及形成在第一 区域和石墨烯膜的第二区域经由栅极绝缘膜。 石墨烯膜用作通道。 在第一区域和第二区域之间的接合处形成肖特基结。 第一区域具有导体特性，第二区域与第一区域的漏电极侧相邻并且具有半导体特性。

公开(公告)号：US09041056B2

公开(公告)日：2015-05-26

申请号：US13346906

申请日：2012-01-10

申请人： Toshitaka Miyata ,  Kanna Adachi ,  Shigeru Kawanaka

发明人： Toshitaka Miyata ,  Kanna Adachi ,  Shigeru Kawanaka

IPC分类号： H01L29/16 ,  H01L29/772 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66

CPC分类号： H01L29/772 ,  H01L29/0895 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7836

摘要： According to one embodiment, a semiconductor device including: a substrate; a gate electrode formed above the substrate; a gate insulating film formed under the gate electrode; a channel layer formed under the gate insulating film by using a channel layer material; a source region and a drain region formed in the substrate so as to interpose the channel layer therebetween in a channel direction; and a source extension layer formed in the substrate between the channel layer and the source region so as to overlap a source-side end portion of the channel layer. The source extension layer forms a heterointerface with the channel layer. The heterointerface is a tunnel channel for carries.

摘要翻译： 根据一个实施例，一种半导体器件包括：衬底; 形成在所述衬底上的栅电极; 形成在栅电极下方的栅极绝缘膜; 通过使用沟道层材料形成在所述栅极绝缘膜下方的沟道层; 源极区域和漏极区域，形成在所述基板中，以在沟道方向上插入所述沟道层; 以及源极延伸层，其形成在沟道层和源极区域之间的衬底中，以与沟道层的源极侧端部重叠。 源延伸层与沟道层形成异质界面。 异步接口是一个用于载波的隧道通道。

公开(公告)号：US20120175637A1

公开(公告)日：2012-07-12

申请号：US13346906

申请日：2012-01-10

申请人： Toshitaka MIYATA ,  Kanna Adachi ,  Shigeru Kawanaka

发明人： Toshitaka MIYATA ,  Kanna Adachi ,  Shigeru Kawanaka

IPC分类号： H01L29/16 ,  H01L21/336

CPC分类号： H01L29/772 ,  H01L29/0895 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7836

摘要： According to one embodiment, a semiconductor device including: a substrate; a gate electrode formed above the substrate; a gate insulating film formed under the gate electrode; a channel layer formed under the gate insulating film by using a channel layer material; a source region and a drain region formed in the substrate so as to interpose the channel layer therebetween in a channel direction; and a source extension layer formed in the substrate between the channel layer and the source region so as to overlap a source-side end portion of the channel layer. The source extension layer forms a heterointerface with the channel layer. The heterointerface is a tunnel channel for carries.

摘要翻译： 根据一个实施例，一种半导体器件包括：衬底; 形成在所述衬底上的栅电极; 形成在栅电极下方的栅极绝缘膜; 通过使用沟道层材料形成在所述栅极绝缘膜下方的沟道层; 源极区域和漏极区域，形成在所述基板中，以在沟道方向上插入所述沟道层; 以及源极延伸层，其形成在沟道层和源极区域之间的衬底中，以与沟道层的源极侧端部重叠。 源延伸层与沟道层形成异质界面。 异步接口是一个用于载波的隧道通道。

公开(公告)号：US08405159B2

公开(公告)日：2013-03-26

申请号：US13234536

申请日：2011-09-16

申请人： Kanna Adachi ,  Shigeru Kawanaka ,  Satoshi Inaba

发明人： Kanna Adachi ,  Shigeru Kawanaka ,  Satoshi Inaba

IPC分类号： H01L27/088

CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L29/4238

摘要： In accordance with an embodiment, a semiconductor device includes an SRAM cell on a substrate. The SRAM cell includes: first and second load transistors each having an n-type source region and a p-type drain region, first and second driver transistors each having a p-type source region and an n-type drain region, and first and second transfer transistors each having an n-type source region and a n-type drain region. The n-type source regions of the first and second load transistors, the n-type drain regions of the first and second driver transistors, and the n-type source regions and the n-type drain regions of the first and second transfer transistors are located in a region other than a region present between any two of the p-type drain regions of the first and second load transistors and the p-type source regions of the first and second driver transistors.

摘要翻译： 根据实施例，半导体器件在衬底上包括SRAM单元。 SRAM单元包括：具有n型源极区域和p型漏极区域的第一和第二负载晶体管，每个具有p型源极区域和n型漏极区域的第一和第二驱动器晶体管，以及第一和第二负极晶体管， 第二传输晶体管，每个具有n型源极区和n型漏极区。 第一和第二负载晶体管的n型源极区域，第一和第二驱动晶体管的n型漏极区域以及第一和第二转移晶体管的n型源极区域和n型漏极区域是 位于除了存在于第一和第二负载晶体管的任何两个p型漏极区域之间的区域以及第一和第二驱动器晶体管的p型源极区域之外的区域中。

公开(公告)号：US20120228706A1

公开(公告)日：2012-09-13

申请号：US13358643

申请日：2012-01-26

申请人： Emiko Sugizaki ,  Shigeru Kawanaka ,  Kanna Adachi

发明人： Emiko Sugizaki ,  Shigeru Kawanaka ,  Kanna Adachi

IPC分类号： H01L29/78

CPC分类号： H01L29/7391 ,  H01L29/0657 ,  H01L29/42312

摘要： A memory includes a semiconductor layer, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film. A first channel region of a first conductivity type is provided on a surface of the semiconductor layer below the gate insulating film. A diffusion layer of a second conductivity type is provided below the first channel region in the semiconductor layer. The diffusion layer contacts a bottom of the first channel region in a direction substantially vertical to a surface of the semiconductor layer. The diffusion layer forms a PN junction with the bottom of the first channel region. A drain of a first conductivity type and a source of a second conductivity type are provided on a side and another side of the first channel region. A sidewall film covers a side surface of the first channel region on a side of the diffusion layer.

摘要翻译： 存储器包括半导体层，半导体层上的栅极绝缘膜和栅极绝缘膜上的栅电极。 第一导电类型的第一沟道区设置在栅极绝缘膜下方的半导体层的表面上。 第二导电类型的扩散层设置在半导体层中的第一沟道区的下方。 扩散层在与半导体层的表面大致垂直的方向上接触第一沟道区的底部。 扩散层与第一通道区域的底部形成PN结。 第一导电类型的漏极和第二导电类型的源极设置在第一沟道区的一侧和另一侧。 侧壁膜覆盖扩散层侧的第一沟道区域的侧表面。

公开(公告)号：US20120091537A1

公开(公告)日：2012-04-19

申请号：US13234536

申请日：2011-09-16

申请人： Kanna Adachi ,  Shigeru Kawanaka ,  Satoshi Inaba

发明人： Kanna Adachi ,  Shigeru Kawanaka ,  Satoshi Inaba

IPC分类号： H01L27/11

CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L29/4238

摘要： In accordance with an embodiment, a semiconductor device includes an SRAM cell on a substrate. The SRAM cell includes: first and second load transistors each having an n-type source region and a p-type drain region, first and second driver transistors each having a p-type source region and an n-type drain region, and first and second transfer transistors each having an n-type source region and a n-type drain region. The n-type source regions of the first and second load transistors, the n-type drain regions of the first and second driver transistors, and the n-type source regions and the n-type drain regions of the first and second transfer transistors are located in a region other than a region present between any two of the p-type drain regions of the first and second load transistors and the p-type source regions of the first and second driver transistors.

摘要翻译： 根据实施例，半导体器件在衬底上包括SRAM单元。 SRAM单元包括：具有n型源极区域和p型漏极区域的第一和第二负载晶体管，每个具有p型源极区域和n型漏极区域的第一和第二驱动器晶体管，以及第一和第二负极晶体管， 第二传输晶体管，每个具有n型源极区和n型漏极区。 第一和第二负载晶体管的n型源极区域，第一和第二驱动晶体管的n型漏极区域以及第一和第二转移晶体管的n型源极区域和n型漏极区域是 位于除了存在于第一和第二负载晶体管的任何两个p型漏极区域之间的区域以及第一和第二驱动器晶体管的p型源极区域之外的区域中。

公开(公告)号：US09041104B2

公开(公告)日：2015-05-26

申请号：US13358643

申请日：2012-01-26

申请人： Emiko Sugizaki ,  Shigeru Kawanaka ,  Kanna Adachi

发明人： Emiko Sugizaki ,  Shigeru Kawanaka ,  Kanna Adachi

IPC分类号： H01L29/78 ,  H01L29/739 ,  H01L29/06 ,  H01L29/423

CPC分类号： H01L29/7391 ,  H01L29/0657 ,  H01L29/42312

摘要： A memory includes a semiconductor layer, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film. A first channel region of a first conductivity type is provided on a surface of the semiconductor layer below the gate insulating film. A diffusion layer of a second conductivity type is provided below the first channel region in the semiconductor layer. The diffusion layer contacts a bottom of the first channel region in a direction substantially vertical to a surface of the semiconductor layer. The diffusion layer forms a PN junction with the bottom of the first channel region. A drain of a first conductivity type and a source of a second conductivity type are provided on a side and another side of the first channel region. A sidewall film covers a side surface of the first channel region on a side of the diffusion layer.

摘要翻译： 存储器包括半导体层，半导体层上的栅极绝缘膜和栅极绝缘膜上的栅电极。 第一导电类型的第一沟道区设置在栅极绝缘膜下方的半导体层的表面上。 第二导电类型的扩散层设置在半导体层中的第一沟道区的下方。 扩散层在与半导体层的表面大致垂直的方向上接触第一沟道区的底部。 扩散层与第一通道区域的底部形成PN结。 第一导电类型的漏极和第二导电类型的源极设置在第一沟道区的一侧和另一侧。 侧壁膜覆盖扩散层侧的第一沟道区域的侧表面。

公开(公告)号：US20110284938A1

公开(公告)日：2011-11-24

申请号：US13053399

申请日：2011-03-22

申请人： Shigeru Kawanaka ,  Kanna Adachi ,  Yoshiyuki Kondo

发明人： Shigeru Kawanaka ,  Kanna Adachi ,  Yoshiyuki Kondo

IPC分类号： H01L29/82

CPC分类号： H01L29/66984 ,  G11C11/16 ,  H01F10/1936

摘要： A spin transistor according to an embodiment includes: a first magnetic region supplying a first polarized signal polarized in a first magnetization direction in accordance with a first input signal; a second magnetic region supplying a second polarized signal polarized in a second magnetization direction opposite from the first magnetization direction in accordance with a second input signal, the second input signal being different from the first input signal; and a third magnetic region outputting the first polarized signal supplied from the first magnetic region in accordance with a third input signal, and outputting the second polarized signal supplied from the second magnetic region in accordance with a fourth input signal different from the third input signal.

摘要翻译： 根据实施例的自旋晶体管包括：第一磁区，根据第一输入信号提供沿第一磁化方向偏振的第一偏振信号; 第二磁区，根据第二输入信号，提供沿与第一磁化方向相反的第二磁化方向偏振的第二极化信号，第二输入信号不同于第一输入信号; 以及第三磁区，根据第三输入信号输出从第一磁区提供的第一极化信号，并根据与第三输入信号不同的第四输入信号输出从第二磁区提供的第二极化信号。

公开(公告)号：US20060157738A1

公开(公告)日：2006-07-20

申请号：US11369041

申请日：2006-03-07

申请人： Shigeru Kawanaka

发明人： Shigeru Kawanaka

IPC分类号： H01L27/10

CPC分类号： H01L21/84 ,  G11C11/405 ,  H01L27/108 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/7841

摘要： According to one aspect of the present invention, a semiconductor memory device has: a semiconductor layer formed on an insulating film; and a memory cell array including a matrix arrangement of a plurality of memory cells each made up of first and second transistors connected in series, one side of each memory cell being connected to a bit line and the other side of each memory cell being supplied with a reference potential, and according to another aspect of the present invention, a semiconductor memory device manufacturing method includes: forming an oxide layer and a silicon active layer on a semiconductor substrate; forming an element isolation region for separating said silicon active layer into discrete element-forming regions to be substantially flush with said silicon active layer; forming gate electrode of paired two transistors by depositing a gate electrode material on said silicon active layer and patterning it; injecting predetermined ions into a region for forming a diffusion layer in, using said gate electrodes as an ion injection mask; forming said paired transistors by activating the injected ions through a heat process; and forming a first gate line connected to the gate electrode of one of said paired transistors and a second gate line connected to the gate electrode of the other of said paired transistors.