公开(公告)号：US20080179659A1

公开(公告)日：2008-07-31

申请号：US12021003

申请日：2008-01-28

申请人： Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Takashi Izumida

发明人： Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Takashi Izumida

IPC分类号： H01L27/115

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device relating to one embodiment of this invention includes a substrate, a plurality of memory strings formed on said substrate, said memory string having a first select gate transistor, a plurality of memory cells and a second select gate transistor, said first select gate transistor having a first pillar semiconductor, a first gate insulation layer formed around said first pillar semiconductor and a first gate electrode being formed around said first gate insulation layer; said memory cell having a second pillar semiconductor, a first insulation layer formed around said second pillar semiconductor, a storage layer formed around said first insulation layer, a second insulation layer formed around said storage layer and first to nth electrodes (n is a natural number 2 or more) being formed around said second insulation layer, said first to nth electrodes being spread in two dimensions respectively, said second select gate transistor having a third pillar semiconductor, a second gate insulation layer formed around said third pillar semiconductor and a second gate electrode being formed around said second gate insulation layer, and a channel region of at least either said first select gate transistor or said second select gate transistor formed by an opposite conductive type semiconductor to a source region and a drain region.

摘要翻译： 关于本发明的一个实施例的非易失性半导体存储器件包括衬底，形成在所述衬底上的多个存储器串，所述存储器串具有第一选择栅晶体管，多个存储单元和第二选择栅晶体管，所述第一 选择具有第一柱状半导体的栅极晶体管，形成在所述第一柱状半导体周围的第一栅极绝缘层和围绕所述第一栅极绝缘层形成的第一栅极电极; 所述存储单元具有第二柱状半导体，围绕所述第二柱状半导体形成的第一绝缘层，围绕所述第一绝缘层形成的存储层，形成在所述存储层和第一至第n电极周围的第二绝缘层（n为自然数） 2个或更多个），所述第一至第n电极分别以两维扩展，所述第二选择栅晶体管具有第三柱半导体，围绕所述第三柱半导体形成的第二栅绝缘层和第二栅极 形成在所述第二栅极绝缘层周围的电极，以及至少所述第一选择栅极晶体管或所述第二选择栅极晶体管的沟道区域，所述沟道区域由相对的导电型半导体形成为源极区域和漏极区域。

公开(公告)号：US20070102749A1

公开(公告)日：2007-05-10

申请号：US11549770

申请日：2006-10-16

申请人： Riichiro Shirota ,  Fumitaka Arai ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunokii ,  Nobutoshi Aoki ,  Makoto Mizukami ,  Kiyotaka Miyano ,  Ichiro Mizushima

发明人： Riichiro Shirota ,  Fumitaka Arai ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunokii ,  Nobutoshi Aoki ,  Makoto Mizukami ,  Kiyotaka Miyano ,  Ichiro Mizushima

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select gate transistors disposed at both ends thereof.

摘要翻译： 半导体存储器件包括：半导体衬底; 在半导体衬底上形成有绝缘膜的半导体层，所述半导体层经由形成在所述绝缘膜中的开口与所述半导体衬底接触; 以及在半导体层上形成有串联连接的多个电可重写和非易失性存储单元的NAND单元单元，以及设置在其两端的第一和第二选择栅晶体管。

公开(公告)号：US06784006B2

公开(公告)日：2004-08-31

申请号：US10001977

申请日：2001-12-05

申请人： Hiroyoshi Tanimoto ,  Toshiyuki Enda

发明人： Hiroyoshi Tanimoto ,  Toshiyuki Enda

IPC分类号： H01L2166

CPC分类号： H01L22/20 ,  G01R31/2642

摘要： A method of manufacturing a semiconductor device, comprises: forming a semiconductor element in a semiconductor active region, and calculating the generation rate of electron hole pairs generated due to impact ionization caused in the semiconductor element; calculating a volume integral of the generation rate at least in an area where the impact ionization is caused; evaluating time-dependent degradations of electrical characteristics of the semiconductor element on the basis of the volume integral; and manufacturing a semiconductor device on the basis of the evaluation.

摘要翻译： 一种制造半导体器件的方法，包括：在半导体有源区中形成半导体元件，并计算由于在半导体元件中引起的冲击电离产生的电子空穴对的产生速率; 至少在造成碰撞电离的区域中计算发电率的体积积分; 基于体积积分来评估半导体元件的电特性的时间依赖性降低; 并在评估的基础上制造半导体器件。

公开(公告)号：US06195790B1

公开(公告)日：2001-02-27

申请号：US09061866

申请日：1998-04-17

申请人： Hiroyoshi Tanimoto ,  Toshiyuki Enda ,  Naoyuki Shigyo ,  Kazuya Matsuzawa

发明人： Hiroyoshi Tanimoto ,  Toshiyuki Enda ,  Naoyuki Shigyo ,  Kazuya Matsuzawa

IPC分类号： G06F760

CPC分类号： G06F17/5018 ,  G06F2217/16

摘要： A &Dgr;Z calculator calculates difference between an inversion layer capacitance by a classical theory and an inversion layer capacitance by a quantum theory, calculates &Dgr;Z which is a thickness of a semiconductor substrate equivalent to the difference in inversion layer capacitance. A discretization mesh generator generates a Delaunay discretization mesh for a structure of the semiconductor device to be evaluated. An electrical parameter calculator calculates electrical parameters of the semiconductor device under constraint that a charge density of channel conductivity type of the semiconductor device is set to zero at discretization mesh points of the discretization mesh on an interface between an insulating film and the semiconductor substrate and at discretization mesh points of the discretization mesh in the semiconductor substrate which are located within a distance less than the stored &Dgr;Z from the interface between the insulating film and the semiconductor substrate.

摘要翻译： DELTAZ计算器通过经典理论计算反演层电容与量子理论的反演层电容之间的差异，计算作为反转层电容差异的半导体衬底的厚度的DELTAZ。 离散网格生成器为要评估的半导体器件的结构生成Delaunay离散化网格。 电参数计算器在绝缘膜和半导体衬底之间的界面上的离散网格的离散网格点处以及半导体衬底的沟道导电类型的电荷密度设置为零的条件下计算半导体器件的电参数，并且在 半导体衬底中离散网格的离散网格点位于比绝缘膜和半导体衬底之间的界面上的存储的DELTAZ小的距离内。

公开(公告)号：US07755134B2

公开(公告)日：2010-07-13

申请号：US11765881

申请日：2007-06-20

申请人： Masaru Kito ,  Nobutoshi Aoki ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaki Kondo ,  Naoki Kusunoki ,  Toshiyuki Enda ,  Sanae Ito ,  Hiroyoshi Tanimoto ,  Hideaki Aochi ,  Akihiro Nitayama ,  Riichiro Shirota

发明人： Masaru Kito ,  Nobutoshi Aoki ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaki Kondo ,  Naoki Kusunoki ,  Toshiyuki Enda ,  Sanae Ito ,  Hiroyoshi Tanimoto ,  Hideaki Aochi ,  Akihiro Nitayama ,  Riichiro Shirota

IPC分类号： H01L27/115

CPC分类号： H01L29/7881 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42336

摘要： A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.

摘要翻译： 非易失性半导体存储器件包括：半导体区域; 器件隔离区域放置在半导体区域中并沿列方向延伸; 放置在半导体区域和器件隔离区之间的半导体层，沿着行方向具有凸形的横截面; 源极/漏极区域放置在半导体层中并彼此间隔开; 位于源极/漏极区之间的半导体层上的栅极绝缘膜; 放置在栅极绝缘膜上的浮栅电极层; 布置在浮栅电极层和器件隔离区的上表面上的隔间绝缘膜; 以及控制栅极电极层，其设置在所述隔间绝缘膜上并沿行方向延伸。

公开(公告)号：US07459748B2

公开(公告)日：2008-12-02

申请号：US11549770

申请日：2006-10-16

申请人： Riichiro Shirota ,  Fumitaka Arai ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Makoto Mizukami ,  Kiyotaka Miyano ,  Ichiro Mizushima

发明人： Riichiro Shirota ,  Fumitaka Arai ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Makoto Mizukami ,  Kiyotaka Miyano ,  Ichiro Mizushima

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select gate transistors disposed at both ends thereof.

摘要翻译： 半导体存储器件包括：半导体衬底; 在半导体衬底上形成有绝缘膜的半导体层，所述半导体层经由形成在所述绝缘膜中的开口与所述半导体衬底接触; 以及在半导体层上形成有串联连接的多个电可重写和非易失性存储单元的NAND单元单元，以及设置在其两端的第一和第二选择栅晶体管。

公开(公告)号：US07393748B2

公开(公告)日：2008-07-01

申请号：US11609614

申请日：2006-12-12

申请人： Fumitaka Arai ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Riichiro Shirota ,  Hiroshi Watanabe ,  Takamitsu Ishihara

发明人： Fumitaka Arai ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Riichiro Shirota ,  Hiroshi Watanabe ,  Takamitsu Ishihara

IPC分类号： H01L21/33

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A NAND cell unit is formed with an advanced gate forming process on a semiconductor layer of a first conductivity type, which is formed on a semiconductor substrate of the first conductivity type with an insulating film interposed therebetween. First impurity-doped layers of a second conductivity type are formed on the semiconductor layer, which serve as channel regions of the select gate transistors Bit line contact- and source line contact-use second impurity-doped layers of the first conductivity type are formed at bit line and source line contact portions, sidewalls of which are covered with an insulating film.

摘要翻译： NAND单元单元在第一导电类型的半导体层上形成有先进的栅极形成工艺，该第一导电类型的半导体层形成在第一导电类型的半导体衬底上，绝缘膜插入其间。 第一导电类型的第一杂质掺杂层形成在用作选择栅晶体管的沟道区的半导体层上。第一导电类型的位线接触和源极接触用第二杂质掺杂层形成在 位线和源极线接触部分，其侧壁被绝缘膜覆盖。

公开(公告)号：US20060237706A1

公开(公告)日：2006-10-26

申请号：US11396507

申请日：2006-04-05

申请人： Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Fumitaka Arai ,  Riichiro Shirota

发明人： Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Fumitaka Arai ,  Riichiro Shirota

IPC分类号： H01L47/00

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile semiconductor memory including a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain-region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.

摘要翻译： 一种包括多个存储单元晶体管的非易失性半导体存储器，所述多个存储单元晶体管中的每一个包括：具有第一导电类型并与支撑衬底上的埋置绝缘层接触的源极区; 具有第一导电类型并与埋入绝缘层接触的漏极区; 以及具有第一导电类型并且设置在源区和漏区之间以与掩埋绝缘层接触的沟道区，其中沟道区的厚度大于1nm且不大于通过将7 nm到存储单元晶体管的栅极长度的一半值。

公开(公告)号：US07539055B2

公开(公告)日：2009-05-26

申请号：US11763204

申请日：2007-06-14

申请人： Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Fumitaka Arai ,  Riichiro Shirota

发明人： Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Fumitaka Arai ,  Riichiro Shirota

IPC分类号： G11C16/04

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile semiconductor memory includes a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.

摘要翻译： 非易失性半导体存储器包括多个存储单元晶体管，多个存储单元晶体管中的每一个包括：具有第一导电类型并与支撑衬底上的埋置绝缘层接触的源极区; 具有第一导电类型并与埋入绝缘层接触的漏极区; 以及具有第一导电类型并且设置在源区和漏区之间以与掩埋绝缘层接触的沟道区，其中沟道区的厚度大于1nm且不大于通过将7 nm到存储单元晶体管的栅极长度的一半值。

公开(公告)号：US07528447B2

公开(公告)日：2009-05-05

申请号：US11396507

申请日：2006-04-05

申请人： Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Fumitaka Arai ,  Riichiro Shirota

发明人： Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Fumitaka Arai ,  Riichiro Shirota

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile semiconductor memory including a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.

摘要翻译： 一种包括多个存储单元晶体管的非易失性半导体存储器，所述多个存储单元晶体管中的每一个包括：具有第一导电类型并与支撑衬底上的埋置绝缘层接触的源极区; 具有第一导电类型并与埋入绝缘层接触的漏极区; 以及具有第一导电类型并且设置在源区和漏区之间以与掩埋绝缘层接触的沟道区，其中沟道区的厚度大于1nm且不大于通过将7 nm到存储单元晶体管的栅极长度的一半值。