公开(公告)号：US08533549B2

公开(公告)日：2013-09-10

申请号：US12697555

申请日：2010-02-01

申请人： Shigeo Kondo ,  Kiyomi Naruke ,  Naoyuki Shigyo

发明人： Shigeo Kondo ,  Kiyomi Naruke ,  Naoyuki Shigyo

IPC分类号： G10R31/28

CPC分类号： G06F11/1044

摘要： A memory system includes: a memory chip group including n chips of a nonvolatile semiconductor memory dividedly managed for each of unit areas having predetermined sizes, an unit area of one chip among the n chips storing an error correction code for a group including unit areas in the other n−1 chips associated with the unit area, and the chip that stores the error correction code being different for each of positions of the unit areas; and an access-destination calculating unit that designates, when data in the unit areas is rewritten, the unit area in which the error correction code of data is stored as a writing destination of rewriting data, and designates an unit area in which data before rewriting is stored as a storage destination of a new error correction code.

摘要翻译： 存储器系统包括：存储器芯片组，其包括对具有预定尺寸的每个单位区域分配管理的非易失性半导体存储器的n个芯片，n个芯片中的一个芯片的单位面积存储用于包括单元区域的组的纠错码 与单位区域相关联的其他n-1个码片，并且存储错误校正码的码片对于单位区域的每个位置是不同的; 以及访问目的地计算单元，当单元区域中的数据被重写时，指定存储数据的纠错码的单位区域作为重写数据的写入目的地，并且指定重写前的数据的单位区域 被存储为新的纠错码的存储目的地。

公开(公告)号：US08503245B2

公开(公告)日：2013-08-06

申请号：US13041041

申请日：2011-03-04

申请人： Kunihiro Yamada ,  Naoyuki Shigyo ,  Michiru Hogyoku ,  Hideto Horii

发明人： Kunihiro Yamada ,  Naoyuki Shigyo ,  Michiru Hogyoku ,  Hideto Horii

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3418

摘要： A non-volatile semiconductor memory device according to one aspect of an embodiment of the present invention includes: a semiconductor substrate; an element region; a plurality of memory cell transistors which each include a control gate electrode; and programming means for programming data to a programming target memory cell transistor by applying a programming voltage to the programming target memory cell transistor. Moreover, the programming means applies a programming voltage incremented stepwise from an initial programming voltage, to the programming target memory cell transistor while applying a constant initial intermediate voltage to memory cell transistors adjacent to the programming target memory cell transistor. Thereafter, the programming means applies an intermediate voltage incremented stepwise from the initial intermediate voltage, to one of the respective memory cells adjacent to the programming target memory cell transistor, while applying a constant final programming voltage to the programming target memory cell transistor.

摘要翻译： 根据本发明的实施例的一个方面的非易失性半导体存储器件包括：半导体衬底; 元素区域 多个存储单元晶体管，其各自包括控制栅电极; 以及通过向编程目标存储单元晶体管施加编程电压将数据编程到编程目标存储单元晶体管的编程装置。 此外，编程装置将从初始编程电压逐步增加的编程电压施加到编程目标存储单元晶体管，同时向与编程目标存储单元晶体管相邻的存储单元晶体管施加恒定的初始中间电压。 此后，编程装置将从初始中间电压逐步增加的中间电压施加到与编程目标存储单元晶体管相邻的各个存储单元之一，同时向编程目标存储单元晶体管施加恒定的最终编程电压。

公开(公告)号：US06956747B1

公开(公告)日：2005-10-18

申请号：US11051729

申请日：2005-02-04

申请人： Naoyuki Shigyo ,  Takayuki Hiraoka ,  Kentaro Watanabe

发明人： Naoyuki Shigyo ,  Takayuki Hiraoka ,  Kentaro Watanabe

IPC分类号： H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/60 ,  H05K1/11 ,  H05K1/14

CPC分类号： H01L24/05 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/60 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014

摘要： There is disclosed a semiconductor device comprising at least one first pad being formed above a substrate and given a first potential, at least one first conductive layer being formed between the first pad and the substrate so as to be electrically connected to the first pad, at least one second pad being formed above the substrate so as to sandwich the at least one first conductive layer between the second pad and the substrate, and given a second potential different from the first potential, at least one second conductive layer being formed between the first and second pads and the substrate so as to be electrically connected to the second pad, and a plurality of insulating layers being stacked on the substrate and at least one of the insulating layers being as an inter-electrode insulator of a capacitance element.

摘要翻译： 公开了一种半导体器件，包括至少一个第一焊盘，其形成在衬底上并具有第一电位，至少一个第一导电层形成在第一焊盘和衬底之间，以便电连接到第一焊盘， 至少一个第二焊盘形成在所述衬底上方，以将所述至少一个第一导电层夹在所述第二焊盘和所述衬底之间，并且给予不同于所述第一电位的第二电位，至少一个第二导电层形成在所述第一 以及第二焊盘和所述衬底，以便电连接到所述第二焊盘，并且多个绝缘层堆叠在所述衬底上，并且所述绝缘层中的至少一个作为电容元件的电极间绝缘体。

公开(公告)号：US06195790B1

公开(公告)日：2001-02-27

申请号：US09061866

申请日：1998-04-17

申请人： Hiroyoshi Tanimoto ,  Toshiyuki Enda ,  Naoyuki Shigyo ,  Kazuya Matsuzawa

发明人： Hiroyoshi Tanimoto ,  Toshiyuki Enda ,  Naoyuki Shigyo ,  Kazuya Matsuzawa

IPC分类号： G06F760

CPC分类号： G06F17/5018 ,  G06F2217/16

摘要： A &Dgr;Z calculator calculates difference between an inversion layer capacitance by a classical theory and an inversion layer capacitance by a quantum theory, calculates &Dgr;Z which is a thickness of a semiconductor substrate equivalent to the difference in inversion layer capacitance. A discretization mesh generator generates a Delaunay discretization mesh for a structure of the semiconductor device to be evaluated. An electrical parameter calculator calculates electrical parameters of the semiconductor device under constraint that a charge density of channel conductivity type of the semiconductor device is set to zero at discretization mesh points of the discretization mesh on an interface between an insulating film and the semiconductor substrate and at discretization mesh points of the discretization mesh in the semiconductor substrate which are located within a distance less than the stored &Dgr;Z from the interface between the insulating film and the semiconductor substrate.

摘要翻译： DELTAZ计算器通过经典理论计算反演层电容与量子理论的反演层电容之间的差异，计算作为反转层电容差异的半导体衬底的厚度的DELTAZ。 离散网格生成器为要评估的半导体器件的结构生成Delaunay离散化网格。 电参数计算器在绝缘膜和半导体衬底之间的界面上的离散网格的离散网格点处以及半导体衬底的沟道导电类型的电荷密度设置为零的条件下计算半导体器件的电参数，并且在 半导体衬底中离散网格的离散网格点位于比绝缘膜和半导体衬底之间的界面上的存储的DELTAZ小的距离内。

公开(公告)号：US4636824A

公开(公告)日：1987-01-13

申请号：US850065

申请日：1986-04-07

申请人： Toshiaki Ikoma ,  Hajime Maeda ,  Hisayoshi Yanai ,  Ryo Dang ,  Naoyuki Shigyo

发明人： Toshiaki Ikoma ,  Hajime Maeda ,  Hisayoshi Yanai ,  Ryo Dang ,  Naoyuki Shigyo

IPC分类号： H01L29/74 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L29/74

摘要： A voltage-control type semiconductor switching device is disclosed which includes a pair of controlled electrodes to which a control voltage signal is supplied, and a semiconductive layer formed between the electrodes so as electrically insulative from the electrodes through insulative layers. The semiconductive layer has a channel region and a carrier-storage region which is substantially nonconductive. The channel region is formed laterally along the longitudinal direction of the electrodes, thereby allowing majority carriers such as electrons of the semiconductive layer to flow in the lateral direction. In the current cut-off mode, the carrier-storage region temporarily stores the carriers which move in the direction of thickness of the semiconductive layer due to the electric field created by the voltage. In the current conduction mode, the carrier-storage region releases the carriers stored therein toward the channel region.

摘要翻译： 公开了一种电压控制型半导体开关器件，其包括一对受控电极，控制电压信号被提供给该电压控制电极，以及形成在电极之间的半导体层，以便通过绝缘层与电极电绝缘。 半导体层具有基本不导电的沟道区和载流子存储区。 通道区域沿着电极的纵向横向地形成，从而允许多数载流子例如半导体层的电子沿横向流动。 在当前截止模式中，载流子存储区域暂时存储由于由电压产生的电场而在半导体层的厚度方向上移动的载流子。 在电流导通模式中，载流子存储区域释放其中存储的载流子朝向沟道区域。

公开(公告)号：US20100329026A1

公开(公告)日：2010-12-30

申请号：US12822703

申请日：2010-06-24

申请人： Mitsutoshi NAKAMURA ,  Takeshi Shimane ,  Michiru Hogyoku ,  Katsuaki Isobe ,  Naoyuki Shigyo

发明人： Mitsutoshi NAKAMURA ,  Takeshi Shimane ,  Michiru Hogyoku ,  Katsuaki Isobe ,  Naoyuki Shigyo

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/26 ,  G11C7/04 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621

摘要： According to one embodiment, a semiconductor memory device includes memory cells, first and second selection transistors, a source line, a temperature monitor, and a source line voltage controller. The memory cells are connected in series between a source of the first selection transistor and a drain of the second selection transistor. The temperature monitor monitors a temperature of the semiconductor substrate. The source line voltage controller applies a voltage to the source line, in a read operation, in such a manner that a potential difference between the source line and the semiconductor substrate increases according to a rise in the temperature monitored by the temperature monitor and that a reverse bias is applied between the source of the second selection transistor and the semiconductor substrate.

摘要翻译： 根据一个实施例，半导体存储器件包括存储器单元，第一和第二选择晶体管，源极线，温度监视器和源极线电压控制器。 存储单元串联连接在第一选择晶体管的源极和第二选择晶体管的漏极之间。 温度监视器监视半导体衬底的温度。 源极线电压控制器在读取操作中以源极线和半导体衬底之间的电位差随着由温度监视器监测的温度的升高而增加的电压施加电压， 在第二选择晶体管的源极和半导体衬底之间施加反向偏压。

公开(公告)号：US20100313101A1

公开(公告)日：2010-12-09

申请号：US12697555

申请日：2010-02-01

申请人： Shigeo Kondo ,  Kiyomi Naruke ,  Naoyuki Shigyo

发明人： Shigeo Kondo ,  Kiyomi Naruke ,  Naoyuki Shigyo

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G06F11/1044

摘要： A memory system includes: a memory chip group including n chips of a nonvolatile semiconductor memory dividedly managed for each of unit areas having predetermined sizes, an unit area of one chip among the n chips storing an error correction code for a group including unit areas in the other n−1 chips associated with the unit area, and the chip that stores the error correction code being different for each of positions of the unit areas; and an access-destination calculating unit that designates, when data in the unit areas is rewritten, the unit area in which the error correction code of data is stored as a writing destination of rewriting data, and designates an unit area in which data before rewriting is stored as a storage destination of a new error correction code.

摘要翻译： 存储器系统包括：存储器芯片组，其包括对具有预定尺寸的每个单位区域分配管理的非易失性半导体存储器的n个芯片，n个芯片中的一个芯片的单位面积存储用于包括单元区域的组的纠错码 与单位区域相关联的其他n-1个码片，并且存储错误校正码的码片对于单位区域的每个位置是不同的; 以及访问目的地计算单元，当单元区域中的数据被重写时，指定存储数据的纠错码的单位区域作为重写数据的写入目的地，并且指定重写前的数据的单位区域 被存储为新的纠错码的存储目的地。

公开(公告)号：US07823114B2

公开(公告)日：2010-10-26

申请号：US12081431

申请日：2008-04-16

申请人： Naoyuki Shigyo ,  Tetsuya Yamaguchi

发明人： Naoyuki Shigyo ,  Tetsuya Yamaguchi

IPC分类号： G06F17/50 ,  H03K19/185 ,  H01L25/00 ,  H01L23/58 ,  H01L23/522

CPC分类号： H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of designing a wiring structure of an LSI is capable of reducing a capacitance variation ratio ΔC/C or a resistance-by-capacitance variation ratio Δ(RC)/(RC) of the wiring structure. The method sets a process-originated variation ratio (δP) for the wiring structure, a tolerance (ξC) for the capacitance variation ratio (ΔC/C), and a tolerance (ξRC) for the resistance-by-capacitance variation ratio (Δ(RC)/(RC)), evaluates a fringe capacitance ratio (F=CF/CP) according to a fringe capacitance CF and parallel-plate capacitance CP of the wiring structure, and determines the wiring structure so that the fringe capacitance ratio (F) may satisfy the following: For ⁢ ⁢  Δ ⁢ ⁢ C C  ≤ ξ C , ⁢ F ≥ δ P ξ C - 1 ( 1 ) For ⁢ ⁢  Δ ⁡ ( RC ) RC  ≤ ξ RC , ⁢ F ≤ ( 1 - δ P ) ⁢ δ P δ P - ξ RC - 1 ( 2 ) The method employs an equivalent-variations condition defined as |ΔC/C|=|Δ(RC)/(RC)| to determine the shape parameters of each wire of the wiring structure.

摘要翻译： 设计LSI的布线结构的方法能够降低布线结构的电容变化率＆Dgr; C / C或电容 - 电容变化率＆amp;（RC）/（RC）。 该方法设置了布线结构的过程起始变化率（δP），电容变化率（＆Dgr; C / C）的公差（＆xgr; C）和电阻的公差（＆xgr RC） 电容变化率（＆Dgr;（RC）/（RC））根据布线结构的边缘电容CF和平行板电容CP评估边缘电容比（F = CF / CP），并确定布线结构 使得条纹电容比（F）可以满足以下条件：ForüüDgr; çC≤＆x x C，F≥δP＆xgr; C-1（1）For唔＆Dgr; ⁡（RC）RC骸≤＆xgr RC，F≤（1-δP）δPδP - ＆xgr; RC-1（2）该方法采用等效变量条件定义为|＆Dgr; C / C | = |＆Dgr;（RC）/（RC）| 以确定布线结构的每根导线的形状参数。

公开(公告)号：US20060059445A1

公开(公告)日：2006-03-16

申请号：US11244294

申请日：2005-10-06

申请人： Naoyuki Shigyo ,  Tetsuya Yamaguchi

发明人： Naoyuki Shigyo ,  Tetsuya Yamaguchi

IPC分类号： G06F17/50

CPC分类号： H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of designing a wiring structure of an LSI is capable of reducing a capacitance variation ratio ΔC/C or a resistance-by-capacitance variation ratio Δ(RC)/(RC) of the wiring structure. The method sets a process-originated variation ratio (δP) for the wiring structure, a tolerance (ξC) for the capacitance variation ratio (ΔC/C), and a tolerance (ξRC) for the resistance-by-capacitance variation ratio (Δ(RC)/(RC)), evaluates a fringe capacitance ratio (F=CF/CP) according to a fringe capacitance CF and parallel-plate capacitance CP of the wiring structure, and determines the wiring structure so that the fringe capacitance ratio (F) may satisfy the following: For ⁢  ΔC C  ≤ ξ ⁢   C ,   ⁢ F ≥ δ P ξ C - 1 ( 1 ) For ⁢  Δ ⁡ ( RC ) RC  ≤ ξ RC ,   ⁢ F ≤ ( 1 - δ P ) ⁢ δ P δ P - ξ RC - 1 ( 2 ) The method employs an equivalent-variations condition defined as |ΔC/C|=|Δ(RC)/(RC)| to determine the shape parameters of each wire of the wiring structure.

摘要翻译： 设计LSI的布线结构的方法能够降低布线结构的电容变化率DeltaC / C或电容电容变化率Delta（RC）/（RC）。 该方法设置用于布线结构的过程起始的变化比（delta> P ），电容变化率（ΔC/ C）的公差（xi> C ），以及 用于电容 - 电容变化率（Delta（RC）/（RC））的公差（xi> RC ）评估边缘电容比（F = C＆lt; / C P P）根据布线结构的边缘电容C SUB和平行板电容C P SUB，并确定布线结构 边缘电容比（F）可以满足以下条件

公开(公告)号：US5760442A

公开(公告)日：1998-06-02

申请号：US536451

申请日：1995-09-29

申请人： Naoyuki Shigyo ,  Toshiyuki Enda

发明人： Naoyuki Shigyo ,  Toshiyuki Enda

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L29/786 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L31/117

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L29/78603 ,  H01L29/78606

摘要： A first silicon oxide layer serving as an insulation layer is formed on a p-type semiconductor substrate. An n.sup.+ -type source and drain regions are formed on the p-type substrate 110 with a spacing therebetween. A channel region is interposed between the source and drain regions. A second silicon oxide layer serving as a gate insulation layer is formed on the channel region. A gate terminal is formed on the second silicon oxide layer. High-concentration p-type regions are formed in the p-type semiconductor substrate under the source and drain regions, respectively.

摘要翻译： 用作绝缘层的第一氧化硅层形成在p型半导体衬底上。 在p型衬底110上形成n +型源极和漏极区，其间具有间隔。 沟道区域介于源区和漏区之间。 用作栅极绝缘层的第二氧化硅层形成在沟道区上。 栅极端子形成在第二氧化硅层上。 在源极和漏极区域的p型半导体衬底中分别形成高浓度p型区域。