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公开(公告)号:US20130342375A1
公开(公告)日:2013-12-26
申请号:US13531090
申请日:2012-06-22
申请人: Troy A. Manning , Troy D. Larsen , Martin L. Culley , Jeffrey L. Meader , Steve G. Bard , Dean C. Eyres
发明人: Troy A. Manning , Troy D. Larsen , Martin L. Culley , Jeffrey L. Meader , Steve G. Bard , Dean C. Eyres
IPC分类号: H03M7/30
CPC分类号: G06F3/0608 , G06F3/0661 , G06F3/0673 , H03M7/30 , H03M7/60 , H03M7/6082
摘要: The present disclosure includes apparatuses and methods for data compression and management. A number of methods include receiving a number of data segments corresponding to a managed unit amount of data, determining a respective compressibility of each of the number of data segments, compressing each of the number of data segments in accordance with its respective determined compressibility, forming a compressed managed unit that includes compressed and/or uncompressed data segments corresponding to the number of data segments corresponding to the managed unit amount of data, and forming a page of data that comprises at least the compressed managed unit.
摘要翻译: 本公开包括用于数据压缩和管理的装置和方法。 多种方法包括接收对应于被管理单元数据量的多个数据段,确定多个数据段中的每一个的相应可压缩性,根据其各自确定的压缩性来压缩数据段中的每一个,形成 压缩的被管理单元,其包括对应于与被管理单元数据量对应的数据段的数量的压缩和/或未压缩数据段,以及形成至少包括压缩的被管理单元的数据页。
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公开(公告)号:US09148172B2
公开(公告)日:2015-09-29
申请号:US13531090
申请日:2012-06-22
申请人: Troy A. Manning , Troy D. Larsen , Martin L. Culley , Jeffrey L. Meader , Steve G. Bard , Dean C. Eyres
发明人: Troy A. Manning , Troy D. Larsen , Martin L. Culley , Jeffrey L. Meader , Steve G. Bard , Dean C. Eyres
IPC分类号: H03M7/30
CPC分类号: G06F3/0608 , G06F3/0661 , G06F3/0673 , H03M7/30 , H03M7/60 , H03M7/6082
摘要: The present disclosure includes apparatuses and methods for data compression and management. A number of methods include receiving a number of data segments corresponding to a managed unit amount of data, determining a respective compressibility of each of the number of data segments, compressing each of the number of data segments in accordance with its respective determined compressibility, forming a compressed managed unit that includes compressed and/or uncompressed data segments corresponding to the number of data segments corresponding to the managed unit amount of data, and forming a page of data that comprises at least the compressed managed unit.
摘要翻译: 本公开包括用于数据压缩和管理的装置和方法。 多种方法包括接收对应于被管理单元数据量的多个数据段,确定多个数据段中的每一个的相应可压缩性,根据其各自确定的压缩性来压缩数据段中的每一个,形成 压缩的被管理单元,其包括对应于与被管理单元数据量对应的数据段的数量的压缩和/或未压缩数据段,以及形成至少包括压缩的被管理单元的数据页。
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公开(公告)号:US20120179853A1
公开(公告)日:2012-07-12
申请号:US12985787
申请日:2011-01-06
IPC分类号: G06F12/10
CPC分类号: G06F12/1045 , G06F12/0246 , G06F12/0292 , G06F12/1009 , G06F12/1027 , G06F2212/1004 , G06F2212/7201 , Y02D10/13
摘要: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.
摘要翻译: 本公开包括用于存储器地址转换的装置,系统和方法。 一个或多个实施例包括存储器阵列和耦合到阵列的控制器。 阵列包括具有多个记录的第一表,其中每个记录包括多个条目,其中每个条目包括对应于阵列中存储的数据段的物理地址和逻辑地址。 控制器包括具有多个记录的第二表,其中每个记录包括多个条目,其中每个条目包括对应于第一表中的记录的物理地址和逻辑地址。 控制器还包括具有多个记录的第三表,其中每个记录包括多个条目,其中每个条目包括对应于第二表中的记录的物理地址和逻辑地址。
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公开(公告)号:US09026887B2
公开(公告)日:2015-05-05
申请号:US13421088
申请日:2012-03-15
CPC分类号: G06F11/1068 , G06F3/061 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F3/0688 , G06F3/0689 , G06F8/44 , G06F11/108 , G06F2211/104 , G11C29/52
摘要: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.
摘要翻译: 本公开包括用于物理页面,逻辑页面和码字对应的装置和方法。 许多方法包括将多个数据的逻辑页面的错误编码为码字的数量并将码字的数量写入存储器的多个物理页面。 数据的逻辑页数可以不同于存储器的物理页数。
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公开(公告)号:US08732557B2
公开(公告)日:2014-05-20
申请号:US13118638
申请日:2011-05-31
IPC分类号: G11C29/00
CPC分类号: G06F11/1068 , G06F11/10 , G06F11/108 , G11C11/5628 , G11C16/0483
摘要: Data protection across multiple memory blocks can include writing a first portion of a codeword in a first memory block and writing a second portion of the codeword in a second memory block. The first memory block and the second memory block can be different memory blocks. The first portion of the codeword can be written in a different location in the first memory block than the second portion of the codeword is written in the second memory block.
摘要翻译: 跨多个存储器块的数据保护可以包括在第一存储器块中写入码字的第一部分并将码字的第二部分写入第二存储器块。 第一存储器块和第二存储器块可以是不同的存储器块。 码字的第一部分可以被写入第一存储块中的不同位置,而不是将码字的第二部分写入第二存储块。
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公开(公告)号:US08417914B2
公开(公告)日:2013-04-09
申请号:US12985787
申请日:2011-01-06
IPC分类号: G06F12/00
CPC分类号: G06F12/1045 , G06F12/0246 , G06F12/0292 , G06F12/1009 , G06F12/1027 , G06F2212/1004 , G06F2212/7201 , Y02D10/13
摘要: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.
摘要翻译: 本公开包括用于存储器地址转换的装置,系统和方法。 一个或多个实施例包括存储器阵列和耦合到阵列的控制器。 阵列包括具有多个记录的第一表,其中每个记录包括多个条目,其中每个条目包括对应于阵列中存储的数据段的物理地址和逻辑地址。 控制器包括具有多个记录的第二表,其中每个记录包括多个条目,其中每个条目包括对应于第一表中的记录的物理地址和逻辑地址。 控制器还包括具有多个记录的第三表,其中每个记录包括多个条目,其中每个条目包括对应于第二表中的记录的物理地址和逻辑地址。
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公开(公告)号:US08732431B2
公开(公告)日:2014-05-20
申请号:US13041402
申请日:2011-03-06
CPC分类号: G06F3/0665 , G06F12/00 , G06F12/0246 , G06F12/0292 , G06F12/04 , G06F12/10 , G06F12/1027 , G06F12/1408 , G06F12/1475 , G06F2212/7201 , G06F2212/7202 , Y02D10/13
摘要: The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.
摘要翻译: 本公开包括用于逻辑地址转换的方法,用于操作存储器系统的方法和存储器系统。 一种这样的方法包括接收与LA相关联的命令,其中LA在LAs的特定范围内,并且使用对应于当写入与范围相关联的数据时跳过的物理位置的数量来将LA转换到存储器中的物理位置 的特定范围以外的。
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公开(公告)号:US20120311406A1
公开(公告)日:2012-12-06
申请号:US13118638
申请日:2011-05-31
IPC分类号: G06F11/10
CPC分类号: G06F11/1068 , G06F11/10 , G06F11/108 , G11C11/5628 , G11C16/0483
摘要: Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location can be different than the first location with respect to the second and the first memory blocks.
摘要翻译: 跨越多个存储器块的数据保护可以包括将码字的第一部分写入第一存储器块的第一位置,并将码字的第二部分写入第二存储器块的第二位置。 第二位置可以不同于第二位置和第一存储块的第一位置。
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公开(公告)号:US20120226887A1
公开(公告)日:2012-09-06
申请号:US13041402
申请日:2011-03-06
CPC分类号: G06F3/0665 , G06F12/00 , G06F12/0246 , G06F12/0292 , G06F12/04 , G06F12/10 , G06F12/1027 , G06F12/1408 , G06F12/1475 , G06F2212/7201 , G06F2212/7202 , Y02D10/13
摘要: The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.
摘要翻译: 本公开包括用于逻辑地址转换的方法,用于操作存储器系统的方法和存储器系统。 一种这样的方法包括接收与LA相关联的命令,其中LA在LAs的特定范围内,并且使用对应于当写入与范围相关联的数据时跳过的物理位置的数量来将LA转换到存储器中的物理位置 的特定范围以外的。
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公开(公告)号:US20130246891A1
公开(公告)日:2013-09-19
申请号:US13421088
申请日:2012-03-15
CPC分类号: G06F11/1068 , G06F3/061 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F3/0688 , G06F3/0689 , G06F8/44 , G06F11/108 , G06F2211/104 , G11C29/52
摘要: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.
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