公开(公告)号：US06566236B1

公开(公告)日：2003-05-20

申请号：US09558941

申请日：2000-04-26

申请人： Tsengyou Syau ,  Guo-Qiang (Patrick) Lo ,  Shih-Ked Lee ,  Chuen-Der Lien ,  Sang-Yun Lee ,  Ching-Kai (Robert) Lin

发明人： Tsengyou Syau ,  Guo-Qiang (Patrick) Lo ,  Shih-Ked Lee ,  Chuen-Der Lien ,  Sang-Yun Lee ,  Ching-Kai (Robert) Lin

IPC分类号： H01L213205

CPC分类号： H01L21/76897 ,  H01L21/28061 ,  H01L21/28114 ,  H01L21/32137

摘要： A novel gate structure and a method of forming the same for a self-aligned contact on a semiconductor substrate. The method includes forming a gate oxide layer on the semiconductor substrate. Then a first conductive layer is formed on the gate oxide layer. Next, a second conductive layer, preferably a refractory metal silicide (e.g. WSix), is formed overlying the first conductive layer. A capping layer is formed overlying the second conductive layer. Then the capping layer is etched to form a patterned capping layer having a lower outside corner. An upper portion of the second conductive layer is selectively dry etched laterally to form a lateral recess under the capping layer to increase etch margin. A lower portion of the second conductive layer is then etched anisotropically down to the first conductive layer along a sidewall approximately vertically aligned with the lower outside corner of the patterned capping layer. The recess has an inward extant from the lower outside corner in a range of between 100-300 Angstroms. Increased etch margin is provided in the gate structure to prevent shorts between contact plugs and gate structures during contact formation.

摘要翻译： 一种新颖的栅极结构及其在半导体衬底上形成自对准接触的方法。 该方法包括在半导体衬底上形成栅氧化层。 然后在栅极氧化物层上形成第一导电层。 接下来，形成第二导电层，优选难熔金属硅化物（例如WSix），覆盖在第一导电层上。 形成覆盖在第二导电层上的覆盖层。 然后对覆盖层进行蚀刻以形成具有较低外角的图案化覆盖层。 第二导电层的上部被横向选择性干蚀刻以在覆盖层下方形成横向凹槽以增加蚀刻余量。 然后，第二导电层的下部沿着与图案化覆盖层的下部外角大致垂直对准的侧壁各向异性地蚀刻到第一导电层。 该凹陷部位在下外角处具有介于100-300埃之间的范围内。 在栅极结构中提供增加的蚀刻余量以防止接触形成期间接触插塞和栅极结构之间的短路。

公开(公告)号：US07582567B1

公开(公告)日：2009-09-01

申请号：US11424333

申请日：2006-06-15

申请人： Tsengyou Syau ,  Shih-Ked Lee ,  Chuen-Der Lien

发明人： Tsengyou Syau ,  Shih-Ked Lee ,  Chuen-Der Lien

IPC分类号： H01L21/302

CPC分类号： H01L21/823814 ,  H01L21/823425 ,  H01L21/823835

摘要： A method for forming CMOS devices on a semiconductor substrate is disclosed in which gate structures are formed within both the core region and the non-core region of the semiconductor substrate. The gate structures include a gate dielectric layer and a gate film stack that includes a conductive layer and an overlying hard mask. The hard mask is then removed from the gate structures in the non-core region. A salicide process is then performed so as to form a silicide layer in the non-core region. A barrier layer is formed that extends over the core region and a pre-metal dielectric film is formed that extends over the barrier layer. A selective etch process is performed so as to form self-aligned contact openings that extend through the pre-metal dielectric film and through the barrier layer in the core region. These openings are then filled with conductive material to form self-aligned contacts in the core region. This produces a CMOS device in the core region that has high device density and includes high-speed CMOS devices the non-core region.

摘要翻译： 公开了一种在半导体衬底上形成CMOS器件的方法，其中栅极结构形成在半导体衬底的芯区域和非芯区域中。 栅极结构包括栅极介电层和包括导电层和上覆硬掩模的栅极膜堆叠。 然后将硬掩模从非芯区域中的栅极结构移除。 然后执行自对准硅化物工艺以在非芯区域中形成硅化物层。 形成在芯区域上延伸的阻挡层，并且形成在阻挡层上延伸的预金属介电膜。 执行选择性蚀刻工艺以形成延伸穿过预金属介电膜并通过芯区域中的阻挡层的自对准接触开口。 然后用导电材料填充这些开口，以在芯区域中形成自对准的触点。 这在芯区域产生具有高器件密度的CMOS器件，并且包括非核心区域的高速CMOS器件。

公开(公告)号：US07098114B1

公开(公告)日：2006-08-29

申请号：US10874980

申请日：2004-06-22

申请人： Tsengyou Syau ,  Shih-Ked Lee ,  Chuen-Der Lien

发明人： Tsengyou Syau ,  Shih-Ked Lee ,  Chuen-Der Lien

IPC分类号： H01L21/331

CPC分类号： H01L21/823814 ,  H01L21/823425 ,  H01L21/823835

摘要： A method for forming CMOS devices on a semiconductor substrate is disclosed in which gate structures are formed within both the core region and the non-core region of the semiconductor substrate. The gate structures include a gate dielectric layer and a gate film stack that includes a conductive layer and an overlying hard mask. The hard mask is then removed from the gate structures in the non-core region. A salicide process is then performed so as to form a silicide layer in the non-core region. A barrier layer is formed that extends over the core region and a pre-metal dielectric film is formed that extends over the barrier layer. A selective etch process is performed so as to form self-aligned contact openings that extend through the pre-metal dielectric film and through the barrier layer in the core region. These openings are then filled with conductive material to form self-aligned contacts in the core region. This produces a CMOS device in the core region that has high device density and includes high-speed CMOS devices the non-core region.

摘要翻译： 公开了一种在半导体衬底上形成CMOS器件的方法，其中栅极结构形成在半导体衬底的芯区域和非芯区域中。 栅极结构包括栅极介电层和包括导电层和上覆硬掩模的栅极膜堆叠。 然后将硬掩模从非芯区域中的栅极结构移除。 然后执行自对准硅化物工艺以在非芯区域中形成硅化物层。 形成在芯区域上延伸的阻挡层，并且形成在阻挡层上延伸的预金属介电膜。 执行选择性蚀刻工艺以形成延伸穿过预金属介电膜并通过芯区域中的阻挡层的自对准接触开口。 然后用导电材料填充这些开口，以在芯区域中形成自对准的触点。 这在芯区域产生具有高器件密度的CMOS器件，并且包括非核心区域的高速CMOS器件。

公开(公告)号：US06534414B1

公开(公告)日：2003-03-18

申请号：US09594328

申请日：2000-06-14

申请人： Kuilong Wang ,  Tsengyou Syau ,  Shih-Ked Lee ,  Chuen-Der Lien

发明人： Kuilong Wang ,  Tsengyou Syau ,  Shih-Ked Lee ,  Chuen-Der Lien

IPC分类号： H01L21302

CPC分类号： H01L21/823842

摘要： The invented method involves separately etching the P and N gate features in a dual-poly gate using dual masks, thereby permitting the etching recipes to be tuned to the differentially responsive P and N materials that form the gate. The method involves a) providing a polysilicon layer of a first type over a first region of a semiconductor substrate; b) providing a polysilicon layer of a second type over a second region of the semiconductor substrate; c) depositing a metallic layer overlying the polysilicon layers in the first and second regions; d) depositing an anti-reflective layer overlying the metallic layer in the first and second regions; e) selectively etching the dielectric hard-mask multi-layer film to form a patterned outer hard-mask multi-layer; f) forming a first photoresist pattern overlying the patterned outer hard-mask multi-layer in the first region; g) first etching the metallic layer and the polysilicon layer of the second type to form a stacked gate structure in the second region; h) forming a second photoresist pattern overlying the patterned outer hard-mask multi-layer in the second region; and i) second etching the metallic layer and the polysilicon layer of the first type to form a stacked gate structure in the first region. Preferably, the first photoresist pattern and the second photoresist pattern define a nominal boundary therebetween, with the patterns having a predefined gap therebetween in a region around the boundary. Alternatively, the dual-mask technique is used on a non-hardmask dual-poly film stack and the top dielectric multi-layer film is replaced by an anti-reflection coating (ARC) film.

摘要翻译： 本发明的方法涉及使用双掩模单独蚀刻双多晶硅栅极中的P和N栅极特征，从而允许将蚀刻配方调谐到形成栅极的差分响应P和N材料。 该方法包括：a）在半导体衬底的第一区域上提供第一类型的多晶硅层; b）在所述半导体衬底的第二区域上提供第二类型的多晶硅层; c）在第一和第二区域中沉积覆盖多晶硅层的金属层; d）在所述第一和第二区域中沉积覆盖所述金属层的抗反射层; e）选择性地蚀刻电介质硬掩模多层膜以形成图案化的外部硬掩模多层; f）在第一区域中形成覆盖图案化的外部硬掩模多层的第一光致抗蚀剂图案; g）首先蚀刻第二类型的金属层和多晶硅层，以在第二区域中形成堆叠栅极结构; h）在所述第二区域中形成覆盖所述图案化的外部硬掩模多层的第二光致抗蚀剂图案; 以及i）第二蚀刻第一类型的金属层和多晶硅层，以在第一区域中形成堆叠栅极结构。 优选地，第一光致抗蚀剂图案和第二光致抗蚀剂图案在其之间限定了标称边界，其中图案在边界周围的区域中具有预定的间隙。 或者，双掩模技术用于非硬掩模双重多层膜堆叠，并且顶部电介质多层膜被抗反射涂层（ARC）膜替代。

公开(公告)号：US5990009A

公开(公告)日：1999-11-23

申请号：US805607

申请日：1997-02-25

申请人： Cheng-Chen Hsueh ,  Shih-Ked Lee ,  Chuen-Der Lien

发明人： Cheng-Chen Hsueh ,  Shih-Ked Lee ,  Chuen-Der Lien

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/302

CPC分类号： H01L23/5329 ,  H01L21/76834 ,  H01L23/5222 ,  H01L2924/0002 ,  Y10S257/908

摘要： A structure and method of maximizing the volume of low dielectric constant material between adjacent traces of a conductive interconnect structure. A semiconductor structure includes a semiconductor substrate, a first insulating layer located over the semiconductor substrate, a conductive interconnect layer having a plurality of conductive traces located over the first insulating layer, and a patterned insulating layer located over the patterned interconnect layer. One or more trenches are formed in the upper surface of the first insulating layer. These trenches, which do not extend completely through the first insulating layer, are located between adjacent traces of the interconnect layer. A dielectric material having a low dielectric constant is located in these trenches, and between adjacent traces of the patterned interconnect layer. The trenches advantageously maximize the volume of low dielectric constant material which is located between the traces.

摘要翻译： 一种使导电互连结构的相邻迹线之间的低介电常数材料的体积最大化的结构和方法。 半导体结构包括半导体衬底，位于半导体衬底上的第一绝缘层，具有位于第一绝缘层上方的多个导电迹线的导电互连层以及位于图案化互连层上方的图案化绝缘层。 一个或多个沟槽形成在第一绝缘层的上表面中。 这些不完全延伸穿过第一绝缘层的沟槽位于互连层的相邻迹线之间。 具有低介电常数的介电材料位于这些沟槽中，并位于图案化互连层的相邻迹线之间。 沟槽有利地使位于迹线之间的低介电常数材料的体积最大化。

公开(公告)号：US07499303B2

公开(公告)日：2009-03-03

申请号：US10950186

申请日：2004-09-24

申请人： Chuen-Der Lien ,  Shih-Ked Lee

发明人： Chuen-Der Lien ,  Shih-Ked Lee

IPC分类号： G11C15/00

CPC分类号： G11C15/046 ,  G11C11/22 ,  G11C13/0004 ,  G11C15/02

摘要： A CAM cell array according to embodiments of the present invention include an array of CAM cells, each of the CAM cells comprising a first cell, the first cell including a non-volatile storage element coupled to at least one first data line and a match line; a match line controller coupled to the match line; and a data line controller coupled to the data lines, wherein a write operation is performed by changing a state of the non-volatile storage element by providing data to the at least one data line, wherein a read operation is performed by determining the state of the non-volatile storage element through the at least one data line, and wherein a comparison operation is performed by applying data to the at least one data line and determining a match condition on the match line.

摘要翻译： 根据本发明的实施例的CAM单元阵列包括CAM单元的阵列，每个CAM单元包括第一单元，第一单元包括耦合到至少一个第一数据线和匹配线的非易失性存储元件 ; 耦合到匹配线的匹配线控制器; 以及耦合到数据线的数据线控制器，其中通过向所述至少一个数据线提供数据来改变所述非易失性存储元件的状态来执行写入操作，其中通过确定所述非易失性存储元件的状态来执行读取操作 所述非易失性存储元件通过所述至少一个数据线，并且其中通过将数据应用于所述至少一条数据线并确定所述匹配线上的匹配条件来执行比较操作。

公开(公告)号：US07214990B1

公开(公告)日：2007-05-08

申请号：US11063704

申请日：2005-02-22

申请人： Shih-Ked Lee ,  Chuen-Der Lien ,  Louis Huang ,  Gaolong Jin ,  Wanqing Cao ,  Guo-Qiang Lo

发明人： Shih-Ked Lee ,  Chuen-Der Lien ,  Louis Huang ,  Gaolong Jin ,  Wanqing Cao ,  Guo-Qiang Lo

IPC分类号： H01L27/11

CPC分类号： H01L28/24 ,  H01L27/016 ,  H01L27/0802 ,  H01L29/78

摘要： The present invention includes SRAM memory cells and methods for forming SRAM cells having reduced soft error rate. The SRAM cell includes a first NMOS transistor and a first PMOS transistor having a common gate, and a second NMOS transistor and a second PMOS transistor having a common gate. A first resistor is electrically coupled on one end to the drains of the first PMOS transistor and the first NMOS transistor; and is electrically coupled on the other end to the common gate of the second NMOS and second PMOS transistors. A second resistor is electrically coupled on one end to the drains of the second PMOS transistor and the second NMOS transistor; and is electrically coupled on the other end to the common gate of the first NMOS transistor and the first PMOS transistor. The added resistor can be embedded in a contact opening such that it does not take up valuable surface area on the semiconductor substrate. Thereby, data loss from soft errors can be avoided while preserving small memory cell size.

摘要翻译： 本发明包括SRAM存储单元和用于形成具有降低的软错误率的SRAM单元的方法。 SRAM单元包括第一NMOS晶体管和具有公共栅极的第一PMOS晶体管，以及具有公共栅极的第二NMOS晶体管和第二PMOS晶体管。 第一电阻器的一端电耦合到第一PMOS晶体管和第一NMOS晶体管的漏极; 并且在另一端电耦合到第二NMOS和第二PMOS晶体管的公共栅极。 第二电阻器的一端电耦合到第二PMOS晶体管和第二NMOS晶体管的漏极; 并且在另一端电耦合到第一NMOS晶体管和第一PMOS晶体管的公共栅极。 添加的电阻器可以嵌入在接触开口中，使得其不占据半导体衬底上的有价值的表面积。 因此，可以避免从软错误的数据丢失，同时保持小的存储单元尺寸。

公开(公告)号：US6136687A

公开(公告)日：2000-10-24

申请号：US978967

申请日：1997-11-26

申请人： Shih-Ked Lee ,  Chu-Tsao Yen ,  Cheng-Chen Calvin Hsueh ,  James R. Shih ,  Chuen-Der Lien

发明人： Shih-Ked Lee ,  Chu-Tsao Yen ,  Cheng-Chen Calvin Hsueh ,  James R. Shih ,  Chuen-Der Lien

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/7682

摘要： A method for manufacturing integrated circuits increases the aspect ratio of the electrical conductor members connected to the circuits by increasing the effective height of the conductors, either by forming a thicker layer of conductor material prior to patterning the conductor members, or by adding a capping dielectric layer to the conductor material prior to patterning, or by overetching the dielectric material underlying the conductor members.The structure is then covered by a dielectric layer having poor step coverage, resulting in a number of voids and open spaces in the dielectric layer to thereby reduce the dielectric constant between the patterned conductors. A plasma etchback of the dielectric layer is employed to open and shape additional voids and open spaces in the dielectric layer. This is followed by the deposition of a second layer of dielectric material to seal the structure, including any open spaces in the first layer of dielectric material.

摘要翻译： 制造集成电路的方法通过增加导体的有效高度来增加与电路连接的电导体部件的纵横比，通过在构图导体部件之前形成较厚的导体材料层，或者通过添加封盖电介质 在图案化之前或通过过蚀刻导体部件下面的电介质材料的层。 然后，该结构被具有差的阶梯覆盖的介电层覆盖，导致介电层中的空隙和开放空间的数量，从而降低图案化导体之间的介电常数。 采用电介质层的等离子体回蚀来打开和形成电介质层中的附加空隙和开放空间。 之后沉积第二层电介质材料以密封结构，包括第一层电介质材料中的任何开放空间。

公开(公告)号：US07921400B1

公开(公告)日：2011-04-05

申请号：US12478734

申请日：2009-06-04

申请人： Chuen-Der Lien ,  Shih-Ked Lee

发明人： Chuen-Der Lien ,  Shih-Ked Lee

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/505

摘要： A cell library is disclosed that includes soft error resistant logic cells. The soft error resistant logic cells can be used along with memory cells and conventional logic cells to form integrated circuit designs having increased soft error resistance. A method for forming an integrated circuit device is disclosed in which a first integrated circuit design is formed using conventional logic cells. An iterative process is then performed in which some of the conventional logic cells are replaced with high soft error resistant logic cells to obtain a soft error resistant design. Each soft error resistant logic cell that replaces a corresponding conventional logic cell will have the same cell size as the cell that is replaced, producing a soft error resistant design that does not take up additional surface area on the semiconductor substrate.

摘要翻译： 公开了包括软错误的逻辑单元的单元库。 软的抗错误逻辑单元可与存储器单元和常规逻辑单元一起使用以形成具有增加的软错误电阻的集成电路设计。 公开了一种用于形成集成电路器件的方法，其中使用常规逻辑单元形成第一集成电路设计。 然后执行一个迭代过程，其中一些常规的逻辑单元被高的软错误抵抗的逻辑单元替换以获得软的抗错误设计。 取代相应的常规逻辑单元的每个软错误抵抗逻辑单元将具有与被替换的单元相同的单元尺寸，从而产生不占用半导体衬底上的附加表面积的柔性抗错误设计。

公开(公告)号：US07560800B1

公开(公告)日：2009-07-14

申请号：US11459820

申请日：2006-07-25

申请人： Chuen-Der Lien ,  Shih-Ked Lee

发明人： Chuen-Der Lien ,  Shih-Ked Lee

IPC分类号： H01L29/06

CPC分类号： H01L23/585 ,  H01L23/552 ,  H01L23/564 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A die seal structure for sealing integrated circuit devices formed on a semiconductor substrate. The die seal structure includes a die seal and a junction diode. The die seal only connects to the semiconductor substrate through the junction diode, thereby reducing noise coupling through the die seal. In another aspect of the present invention the die seal structure includes a die seal and a bipolar structure. In this embodiment the die seal only connects to the semiconductor substrate through the bipolar structure.

摘要翻译： 一种用于密封形成在半导体衬底上的集成电路器件的模封密封结构。 模具密封结构包括模具密封和结二极管。 管芯密封件仅通过结二极管连接到半导体衬底，从而减少通过管芯密封件的噪声耦合。 在本发明的另一方面，模具密封结构包括模具密封件和双极结构。 在该实施例中，管芯密封件仅通过双极结构连接到半导体衬底。