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    Gate structures with increased etch margin for self-aligned contact and the method of forming the same
    1.
    发明授权
    Gate structures with increased etch margin for self-aligned contact and the method of forming the same 失效
    具有增加的用于自对准接触的蚀刻余量的栅极结构及其形成方法

    公开(公告)号：US06566236B1

    公开(公告)日：2003-05-20

    申请号：US09558941

    申请日：2000-04-26

    申请人： Tsengyou Syau ,  Guo-Qiang (Patrick) Lo ,  Shih-Ked Lee ,  Chuen-Der Lien ,  Sang-Yun Lee ,  Ching-Kai (Robert) Lin

    发明人： Tsengyou Syau ,  Guo-Qiang (Patrick) Lo ,  Shih-Ked Lee ,  Chuen-Der Lien ,  Sang-Yun Lee ,  Ching-Kai (Robert) Lin

    IPC分类号： H01L213205

    CPC分类号： H01L21/76897 ,  H01L21/28061 ,  H01L21/28114 ,  H01L21/32137

    摘要： A novel gate structure and a method of forming the same for a self-aligned contact on a semiconductor substrate. The method includes forming a gate oxide layer on the semiconductor substrate. Then a first conductive layer is formed on the gate oxide layer. Next, a second conductive layer, preferably a refractory metal silicide (e.g. WSix), is formed overlying the first conductive layer. A capping layer is formed overlying the second conductive layer. Then the capping layer is etched to form a patterned capping layer having a lower outside corner. An upper portion of the second conductive layer is selectively dry etched laterally to form a lateral recess under the capping layer to increase etch margin. A lower portion of the second conductive layer is then etched anisotropically down to the first conductive layer along a sidewall approximately vertically aligned with the lower outside corner of the patterned capping layer. The recess has an inward extant from the lower outside corner in a range of between 100-300 Angstroms. Increased etch margin is provided in the gate structure to prevent shorts between contact plugs and gate structures during contact formation.

    摘要翻译： 一种新颖的栅极结构及其在半导体衬底上形成自对准接触的方法。 该方法包括在半导体衬底上形成栅氧化层。 然后在栅极氧化物层上形成第一导电层。 接下来，形成第二导电层，优选难熔金属硅化物（例如WSix），覆盖在第一导电层上。 形成覆盖在第二导电层上的覆盖层。 然后对覆盖层进行蚀刻以形成具有较低外角的图案化覆盖层。 第二导电层的上部被横向选择性干蚀刻以在覆盖层下方形成横向凹槽以增加蚀刻余量。 然后，第二导电层的下部沿着与图案化覆盖层的下部外角大致垂直对准的侧壁各向异性地蚀刻到第一导电层。 该凹陷部位在下外角处具有介于100-300埃之间的范围内。 在栅极结构中提供增加的蚀刻余量以防止接触形成期间接触插塞和栅极结构之间的短路。

    Cobalt silicide structure for improving gate oxide integrity and method for fabricating same
    2.
    发明授权
    Cobalt silicide structure for improving gate oxide integrity and method for fabricating same 失效
    用于提高栅极氧化物完整性的硅化钴结构及其制造方法

    公开(公告)号：US06281102B1

    公开(公告)日：2001-08-28

    申请号：US09484580

    申请日：2000-01-13

    申请人： Wanqing Cao ,  Sang-Yun Lee ,  Guo-Qiang Lo ,  Shih-Ked Lee

    发明人： Wanqing Cao ,  Sang-Yun Lee ,  Guo-Qiang Lo ,  Shih-Ked Lee

    IPC分类号： H01L213205

    CPC分类号： H01L29/665 ,  H01L21/28518

    摘要： An improved method is provided for fabricating a cobalt silicide structure that includes the steps of: (1) forming a silicon structure, wherein a native oxide is located over a first surface of the silicon structure, (2) loading the silicon structure into a chamber, (3) introducing a vacuum to the chamber, (4) depositing a titanium layer over the first surface of the silicon structure, wherein the thickness of the titanium layer is selected to remove substantially all of the native oxide, (5) depositing a cobalt layer over the titanium layer, (6) depositing an oxygen impervious cap layer over the cobalt layer; and then (7) breaking the vacuum in the chamber, and (8) subjecting the silicon structure, the titanium layer, the cobalt layer and the cap layer to an anneal, thereby forming the cobalt silicide structure. The cap layer can be, for example, titanium or titanium nitride. The resulting cobalt silicide structure is substantially free from oxygen (i.e., oxide). Consequently, an underlying gate oxide or substrate is advantageously protected from the effects of cobalt silicide spiking.

    摘要翻译： 提供了一种用于制造钴硅化物结构的改进方法，其包括以下步骤：（1）形成硅结构，其中自然氧化物位于硅结构的第一表面上，（2）将硅结构加载到室中 （3）向腔室引入真空，（4）在硅结构的第一表面上沉积钛层，其中选择钛层的厚度以去除基本上所有的天然氧化物，（5）沉积 钴层，（6）在钴层上沉积不透氧的盖层; 然后（7）破坏腔室中的真空，（8）对硅结构，钛层，钴层和盖层进行退火，从而形成钴硅化物结构。 盖层可以是例如钛或氮化钛。 所得的钴硅化物结构基本上不含氧（即氧化物）。 因此，有利地保护下面的栅极氧化物或衬底免受硅化钴尖峰的影响。

    Structures for Novel Three-Dimensional Nonvolatile Memory
    4.
    发明申请
    Structures for Novel Three-Dimensional Nonvolatile Memory 有权

    公开(公告)号：US20220392913A1

    公开(公告)日：2022-12-08

    申请号：US17340371

    申请日：2021-06-07

    申请人： Sang-Yun Lee

    发明人： Sang-Yun Lee

    IPC分类号： H01L27/11573 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11578

    摘要： Disclosed are novel structures and methods for 3D NVM built with vertical transistors above a logic layer. A first embodiment has a conductive film under the transistors and serving as a common node in a memory block. The conductive film may be from a semiconductor layer used to build the transistors. Metal lines are disposed above the transistors for connection through 3D vias to underlying circuitry. Contact plugs may be formed between transistors and metal lines. The conductive film may be coupled to underlying circuitry through contacts on the conductive film or through interconnect vias underneath the film. A second embodiment has conductive lines disposed under the transistors. Either of conductive lines and metal lines may serve as source lines and the other as bit lines for the memory. For low parasitic resistances, the conductive lines may be shorted to bypass metal lines residing in underlying logic layer.

    Methods for Novel Three-Dimensional Nonvolatile Memory
    5.
    发明申请
    Methods for Novel Three-Dimensional Nonvolatile Memory 有权

    公开(公告)号：US20220392910A1

    公开(公告)日：2022-12-08

    申请号：US17347237

    申请日：2021-06-14

    申请人： Sang-Yun Lee

    发明人： Sang-Yun Lee

    IPC分类号： H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  G11C5/06 ,  H01L23/48

    摘要： Disclosed are novel structures and methods for 3D NVM built with vertical transistors above a logic layer. A first embodiment has a conductive film under the transistors and serving as a common node in a memory block. The conductive film may be from a semiconductor layer used to build the transistors. Metal lines are disposed above the transistors for connection through 3D vias to underlying circuitry. Contact plugs may be formed between transistors and metal lines. The conductive film may be coupled to underlying circuitry through contacts on the conductive film or through interconnect vias underneath the film. A second embodiment has conductive lines disposed under the transistors. Either of conductive lines and metal lines may serve as source lines and the other as bit lines for the memory. For low parasitic resistances, the conductive lines may be shorted to bypass metal lines residing in underlying logic layer.

    Novel Three-Dimensional DRAM Structures
    6.
    发明申请
    Novel Three-Dimensional DRAM Structures 有权

    公开(公告)号：US20220139918A1

    公开(公告)日：2022-05-05

    申请号：US17084420

    申请日：2020-10-29

    申请人： Sang-Yun Lee

    发明人： Sang-Yun Lee

    IPC分类号： H01L27/108 ,  H01L29/78

    摘要： Novel three-dimensional DRAM structures are disclosed, together with methods of making the same. Each DRAM cell comprises a vertical transistor and a storage capacitor stacked vertically. Storage capacitors are arranged in a rectangular pattern in the array of DRAM cells. This arrangement improves the area efficiency of storage capacitors over honeycomb type. A first embodiment of the present disclosure uses cup-shaped storage capacitors. The exterior of the cup as well as the interior may contribute to the capacitance. In a second embodiment, a single capacitor pillar forms the internal electrode of each storage capacitor. A third embodiment employs double-pillar storage capacitors. Common to all embodiments are options to dispose contact plugs between vertical transistors and storage capacitors, dispose an etch-stop layer over the gate of vertical transistors, dispose one or more mesh layers for storage capacitors, and widen semiconductor pillars within available space in bit-line direction.

    Structures of Gate Contact Formation for Vertical Transistors
    7.
    发明申请
    Structures of Gate Contact Formation for Vertical Transistors 有权

    公开(公告)号：US20220130973A1

    公开(公告)日：2022-04-28

    申请号：US17083026

    申请日：2020-10-28

    申请人： Sang-Yun Lee

    发明人： Sang-Yun Lee

    IPC分类号： H01L29/423 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/108 ,  H01L27/11573 ,  H01L25/18 ,  H01L29/40 ,  H01L29/66 ,  H01L29/792 ,  H01L29/78

    摘要： Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

    Apparatus for processing exhaust fluid
    8.
    发明授权
    Apparatus for processing exhaust fluid 有权
    废气处理装置

    公开(公告)号：US09494065B2

    公开(公告)日：2016-11-15

    申请号：US13976328

    申请日：2011-12-27

    申请人： Sang-Yun Lee ,  Myung Keun Noh ,  Heaungshig Oh

    发明人： Sang-Yun Lee ,  Myung Keun Noh ,  Heaungshig Oh

    IPC分类号： F01N3/08 ,  B01D53/32 ,  H01L21/67 ,  H05H1/24

    CPC分类号： F01N3/0892 ,  B01D53/32 ,  B01D2257/2025 ,  B01D2257/2027 ,  B01D2257/2047 ,  B01D2258/0216 ,  B01D2259/818 ,  H01L21/67017 ,  H05H1/2406 ,  H05H2001/2456 ,  H05H2245/1215

    摘要： Provided is an apparatus for processing exhaust fluid in which a fluid generated in a process chamber of an apparatus for manufacturing a semiconductor, a display panel, or a solar cell is ejected to the outside. The apparatus for processing exhaust fluid includes: a vacuum pump that is connected to the process chamber, vacuumizes the inside of the process chamber, and ejects the fluid generated in the process chamber to the outside; and a plasma reactor in which plasma is formed and the fluid generated in the process chamber decomposes, wherein the plasma reactor includes: an insulating conduit that is provided between the process chamber and the vacuum pump and provides a space in which the fluid decomposes; at least one electrode unit that is provided on the outer circumferential surface of the conduit and receives a voltage to form the plasma; a buffer unit that is formed of an electrically conductive elastic substance and is disposed between the conduit and the electrode unit to attach the conduit and the electrode unit closely together; and an external pipe into which the conduit, electrode unit and buffer unit are inserted with sealing flanges provided on both end portions of the conduit and external pipe to seal a space between the conduit and the external pipe to prevent fluid process by-products from leaking out should the conduit crack or is damaged.

    摘要翻译： 本发明提供一种处理废液的装置，其中在半导体制造装置，显示面板或太阳能电池的处理室中产生的流体喷射到外部。 用于处理废气流体的装置包括：真空泵，其连接到处理室，对处理室的内部进行真空化，并将处理室中产生的流体喷射到外部; 以及其中形成等离子体并且在处理室中产生的流体分解的等离子体反应器，其中等离子体反应器包括：设置在处理室和真空泵之间并提供流体分解的空间的绝缘导管; 至少一个电极单元，其设置在所述导管的外周面上并接收电压以形成所述等离子体; 缓冲单元，其由导电弹性物质形成并且设置在所述导管和所述电极单元之间，以将所述导管和所述电极单元紧密地附接在一起; 以及管道，电极单元和缓冲单元插入其中的外管，其中设置在导管和外管的两端部上的密封凸缘以密封导管和外管之间的空间，以防止流体加工副产物泄漏 如果管道破裂或损坏。

    Thermal insulator using closed cell expanded perlite
    10.
    发明授权
    Thermal insulator using closed cell expanded perlite 有权
    隔热材料采用闭孔膨胀珍珠岩

    公开(公告)号：US09011708B2

    公开(公告)日：2015-04-21

    申请号：US13582726

    申请日：2011-03-03

    申请人： Bum-Gyu Baek ,  Sang-Yun Lee

    发明人： Bum-Gyu Baek ,  Sang-Yun Lee

    IPC分类号： H01B3/02 ,  H01B3/48 ,  C04B38/00 ,  C04B14/38 ,  C04B26/02 ,  C04B14/18 ,  C04B28/02 ,  B28B23/00 ,  C04B28/26 ,  C04B111/28

    CPC分类号： C04B26/02 ,  B28B23/0087 ,  C04B14/185 ,  C04B28/02 ,  C04B28/26 ,  C04B2111/28 ,  Y02W30/94 ,  Y10S106/02 ,  C04B20/1051 ,  C04B20/0048 ,  C04B14/42 ,  C04B38/0061 ,  C04B14/022 ,  C04B14/4637 ,  C04B18/146 ,  C04B40/0071 ,  C04B40/0263 ,  C04B14/46 ,  C04B14/386

    摘要： The present invention relates to a thermal insulator using closed cell expanded perlite. The thermal insulator using closed cell expanded perlite of the present invention includes: expanded perlite 10 to 84 wt %ç, including dried and expanded perlite ore particles, having a surface with a closed cell shape, as an active ingredient; a liquid binder 15 to 85 wt %; and a reinforcing fiber 0.25 to 5 wt %. Accordingly, the present invention provides a thermal insulator, which enhances the rigidity of expanded perlite, minimizes porosity and gaps between the expanded perlite particles, by reducing compression ratio during compression molding, which results in lower density, improves constructability by lowering thermal conductivity, reduces material and energy costs and can reduce the area required for equipment installation by reducing the thickness of the thermal insulator.

    摘要翻译： 本发明涉及一种使用闭孔膨胀珍珠岩的绝热体。 使用本发明的闭孔膨胀珍珠岩的热绝缘体包括：膨胀珍珠岩10〜84重量％ç，包括具有闭孔形状的表面作为活性成分的干燥膨胀珍珠岩矿石颗粒; 15〜85重量％的液体粘合剂; 和0.25〜5重量％的增强纤维。 因此，本发明提供了一种隔热材料，其通过降低压缩成型时的压缩比来提高膨胀珍珠岩的刚性，使膨胀珍珠岩颗粒之间的孔隙率和间隙最小化，这导致较低的密度，通过降低热导率来改善构造性，减少 材料和能源成本，并且可以通过减小绝热体的厚度来减少设备安装所需的面积。