公开(公告)号：US08543078B2

公开(公告)日：2013-09-24

申请号：US13076871

申请日：2011-03-31

Applicant: Osamu Anegawa ,  Osamu Baba ,  Miki Kubota ,  Tsuneo Tokumitsu

Inventor： Osamu Anegawa ,  Osamu Baba ,  Miki Kubota ,  Tsuneo Tokumitsu

IPC: H04B1/40

CPC classification number: H03D7/1441 ,  H03C2200/0033 ,  H03D7/1433 ,  H03D7/1466 ,  H03D7/1475 ,  H03D7/1483 ,  H03D2200/0023

Abstract: A circuit includes: a first line to which input and output signal terminals are connected; a first transistor having a first terminal connected to the first line, a second terminal connected to a ground potential, and a control terminal supplied with a first oscillation signal, the first transistor outputting the first signal and its harmonic component; a second transistor having a first terminal connected to the first line, a second terminal connected to the ground potential, and a control terminal supplied with a second oscillation signal, the second transistor outputting the second signal and its harmonic component; a first harmonic generator connected to the control terminal of the first transistor and generates a harmonic component including the harmonic component by the first transistor; and a second harmonic generator connected to the control terminal of the second transistor and generates a harmonic component including the harmonic component by the second transistor.

Abstract translation: 电路包括：连接输入和输出信号端子的第一行; 第一晶体管，其具有连接到第一线的第一端子，连接到地电位的第二端子和被提供有第一振荡信号的控制端子，所述第一晶体管输出第一信号及其谐波分量; 第二晶体管，其具有连接到第一线的第一端子，连接到地电位的第二端子和被提供有第二振荡信号的控制端子，所述第二晶体管输出第二信号及其谐波分量; 连接到第一晶体管的控制端的一次谐波发生器，并产生包括第一晶体管的谐波分量的谐波分量; 以及连接到第二晶体管的控制端子的二次谐波发生器，并且通过第二晶体管产生包括谐波分量的谐波分量。

公开(公告)号：US20080048764A1

公开(公告)日：2008-02-28

申请号：US11878707

申请日：2007-07-26

Applicant: Tsuneo Tokumitsu ,  Osamu Baba

Inventor： Tsuneo Tokumitsu ,  Osamu Baba

IPC: G05F1/10

CPC classification number: H03B19/14 ,  H03B7/00 ,  H03B7/06 ,  H03B7/14 ,  H03B2200/0062

Abstract: An electronic circuit device includes a negative resistance generating circuit, a second transistor and a path. The negative resistance generating circuit has a first transistor having a control terminal coupled to a resonator. The second transistor has a control terminal coupled to an output terminal of the first transistor and has an output terminal coupled to a DC bias terminal. The path is coupled to between the DC bias terminal and an output terminal of the first transistor through the second transistor and provides a bias to the first transistor.

Abstract translation: 电子电路装置包括负电阻发生电路，第二晶体管和路径。 负电阻产生电路具有第一晶体管，其具有耦合到谐振器的控制端。 第二晶体管具有耦合到第一晶体管的输出端子的控制端子，并且具有耦合到DC偏置端子的输出端子。 该路径通过第二晶体管耦合到DC偏置端子与第一晶体管的输出端子之间，并向第一晶体管提供偏置。

公开(公告)号：US08264279B2

公开(公告)日：2012-09-11

申请号：US13013291

申请日：2011-01-25

Applicant: Osamu Anegawa ,  Osamu Baba ,  Miki Kubota ,  Tsuneo Tokumitsu

Inventor： Osamu Anegawa ,  Osamu Baba ,  Miki Kubota ,  Tsuneo Tokumitsu

IPC: H03F3/60 ,  H03F3/191

CPC classification number: H03F3/601 ,  H03F2200/405 ,  H03F2200/411

Abstract: An electronic circuit includes a first transistor having a first terminal grounded, a second transistor having a control terminal coupled with a second terminal of the first transistor, a first terminal grounded via a first capacitor, and a second terminal to which a DC power supply is connected, a first distributed constant line having one end connected to a first node between the second terminal of the first transistor and the control terminal of the second transistor and another end grounded via a second capacitor, a second distributed constant line having one end connected to the second terminal of the first transistor and another end connected to the first node, a third distributed constant line having one end connected to the control terminal of the second transistor and another end connected to the first node, a resistor connected between a second node between the first line and the second capacitor and a third node between the first terminal of the second transistor and the first capacitor, and a path that connects the third node and the second terminal of the first transistor via the first line and the resistor in a DC circuit operation.

Abstract translation: 电子电路包括第一晶体管，其第一端接地，第二晶体管，具有与第一晶体管的第二端耦合的控制端，通过第一电容接地的第一端和直流电源的第二端 连接的第一分布常数线，其一端连接到第一晶体管的第二端子与第二晶体管的控制端子之间的第一节点，另一端经由第二电容器接地;第二分布常数线路，其一端连接到 第一晶体管的第二端子和连接到第一节点的另一端，第三分布常数线路，其一端连接到第二晶体管的控制端子，另一端连接到第一节点，电阻器连接在第二节点之间， 第一线路和第二电容器以及第二晶体管的第一端子与冷杉之间的第三节点 以及在直流电路操作中经由第一线连接第一晶体管的第三节点和第二端子和电阻器的路径。

公开(公告)号：US20110241739A1

公开(公告)日：2011-10-06

申请号：US13076871

申请日：2011-03-31

Applicant: Osamu Anegawa ,  Osamu Baba ,  Miki Kubota ,  Tsuneo Tokumitsu

Inventor： Osamu Anegawa ,  Osamu Baba ,  Miki Kubota ,  Tsuneo Tokumitsu

IPC: H03B19/14

CPC classification number: H03D7/1441 ,  H03C2200/0033 ,  H03D7/1433 ,  H03D7/1466 ,  H03D7/1475 ,  H03D7/1483 ,  H03D2200/0023

Abstract: A circuit includes: a first line to which input and output signal terminals are connected; a first transistor having a first terminal connected to the first line, a second terminal connected to a ground potential, and a control terminal supplied with a first oscillation signal, the first transistor outputting the first signal and its harmonic component; a second transistor having a first terminal connected to the first line, a second terminal connected to the ground potential, and a control terminal supplied with a second oscillation signal, the second transistor outputting the second signal and its harmonic component; a first harmonic generator connected to the control terminal of the first transistor and generates a harmonic component including the harmonic component by the first transistor; and a second harmonic generator connected to the control terminal of the second transistor and generates a harmonic component including the harmonic component by the second transistor.

Abstract translation: 电路包括：连接输入和输出信号端子的第一行; 第一晶体管，其具有连接到第一线的第一端子，连接到地电位的第二端子和被提供有第一振荡信号的控制端子，所述第一晶体管输出第一信号及其谐波分量; 第二晶体管，其具有连接到第一线的第一端子，连接到地电位的第二端子和被提供有第二振荡信号的控制端子，所述第二晶体管输出第二信号及其谐波分量; 连接到第一晶体管的控制端的一次谐波发生器，并产生包括第一晶体管的谐波分量的谐波分量; 以及连接到第二晶体管的控制端子的二次谐波发生器，并且通过第二晶体管产生包括谐波分量的谐波分量。

公开(公告)号：US06529051B2

公开(公告)日：2003-03-04

申请号：US09793695

申请日：2001-02-27

Applicant: Tsuneo Tokumitsu ,  Osamu Baba

Inventor： Tsuneo Tokumitsu ,  Osamu Baba

IPC: H03B1900

CPC classification number: H03B19/00

Abstract: A damping resistance 20 is connected between the drain D of an FET 10 and a first end T3 of an output transmission line 13, and a damping resistance 21 is connected between the drain D of an FET 11 and the first end T3. The source of the FET 10 and the gate of the FET 11 are connected to a ground plane on the back surface of a substrate through a via which has a parasitic inductance when a multiplied frequency exceeds 20 GHz. The gate of the FET 10 and the source of the FET 11 receive microwaves of the same frequency and phase through an input transmission line 12.

Abstract translation: 阻尼电阻20连接在FET10的漏极D和输出传输线13的第一端T3之间，阻尼电阻21连接在FET 11的漏极D和第一端T3之间。 FET10的源极和FET11的栅极通过在倍频超过20GHz时具有寄生电感的通孔连接到衬底的背面上的接地面。 FET10的栅极和FET11的源极通过输入传输线12接收相同频率和相位的微波。

公开(公告)号：US07561001B2

公开(公告)日：2009-07-14

申请号：US11878707

申请日：2007-07-26

Applicant: Tsuneo Tokumitsu ,  Osamu Baba

Inventor： Tsuneo Tokumitsu ,  Osamu Baba

IPC: H03B5/08

CPC classification number: H03B19/14 ,  H03B7/00 ,  H03B7/06 ,  H03B7/14 ,  H03B2200/0062

Abstract: An electronic circuit device includes a negative resistance generating circuit, a second transistor and a path. The negative resistance generating circuit has a first transistor having a control terminal coupled to a resonator. The second transistor has a control terminal coupled to an output terminal of the first transistor and has an output terminal coupled to a DC bias terminal. The path is coupled to between the DC bias terminal and an output terminal of the first transistor through the second transistor and provides a bias to the first transistor.

Abstract translation: 电子电路装置包括负电阻发生电路，第二晶体管和路径。 负电阻产生电路具有第一晶体管，其具有耦合到谐振器的控制端。 第二晶体管具有耦合到第一晶体管的输出端子的控制端子，并且具有耦合到DC偏置端子的输出端子。 该路径通过第二晶体管耦合到DC偏置端子与第一晶体管的输出端子之间，并向第一晶体管提供偏置。

公开(公告)号：US20110181363A1

公开(公告)日：2011-07-28

申请号：US13013291

申请日：2011-01-25

Applicant: Osamu Anegawa ,  Osamu Baba ,  Miki Kubota ,  Tsuneo Tokumitsu

Inventor： Osamu Anegawa ,  Osamu Baba ,  Miki Kubota ,  Tsuneo Tokumitsu

IPC: H03F3/60

CPC classification number: H03F3/601 ,  H03F2200/405 ,  H03F2200/411

Abstract: An electronic circuit includes a first transistor having a first terminal grounded, a second transistor having a control terminal coupled with a second terminal of the first transistor, a first terminal grounded via a first capacitor, and a second terminal to which a DC power supply is connected, a first distributed constant line having one end connected to a first node between the second terminal of the first transistor and the control terminal of the second transistor and another end grounded via a second capacitor, a second distributed constant line having one end connected to the second terminal of the first transistor and another end connected to the first node, a third distributed constant line having one end connected to the control terminal of the second transistor and another end connected to the first node, a resistor connected between a second node between the first line and the second capacitor and a third node between the first terminal of the second transistor and the first capacitor, and a path that connects the third node and the second terminal of the first transistor via the first line and the resistor in a DC circuit operation.

Abstract translation: 电子电路包括第一晶体管，其第一端接地，第二晶体管，具有与第一晶体管的第二端耦合的控制端，通过第一电容接地的第一端和直流电源的第二端 连接的第一分布常数线，其一端连接到第一晶体管的第二端子与第二晶体管的控制端子之间的第一节点，另一端经由第二电容器接地;第二分布常数线路，其一端连接到 第一晶体管的第二端子和连接到第一节点的另一端，第三分布常数线路，其一端连接到第二晶体管的控制端子，另一端连接到第一节点，电阻器连接在第二节点之间， 第一线路和第二电容器以及第二晶体管的第一端子与冷杉之间的第三节点 以及在直流电路操作中经由第一线连接第一晶体管的第三节点和第二端子和电阻器的路径。

公开(公告)号：US06600381B2

公开(公告)日：2003-07-29

申请号：US09814753

申请日：2001-03-23

Applicant: Tsuneo Tokumitsu ,  Osamu Baba

Inventor： Tsuneo Tokumitsu ,  Osamu Baba

IPC: H01P708

CPC classification number: H03B5/1847

Abstract: A negative resistance circuit having an output terminal is connected to a first terminal of a strip shaped resonator. Anode of a variable capacitance diode is connected to a second terminal of the strip shaped resonator via a capacitor 1′. Cathode of the variable capacitance diode is grounded. One terminal of a high impedance strip shaped line is connected to the anode of the variable capacitance diode. Other terminal of the strip shaped line is grounded via a capacitor 4. The capacitor 4 has sufficiently low impedance at an oscillation frequency.

Abstract translation: 具有输出端子的负电阻电路连接到带状谐振器的第一端子。 可变电容二极管的阳极通过电容器1'连接到带状谐振器的第二端子。 可变电容二极管的阴极接地。 高阻抗条状线的一个端子连接到可变电容二极管的阳极。 带状线的其他端子通过电容器4接地。电容器4在振荡频率下具有足够低的阻抗。

公开(公告)号：US06747299B2

公开(公告)日：2004-06-08

申请号：US10090633

申请日：2002-03-06

Applicant: Yutaka Mimino ,  Osamu Baba ,  Yoshio Aoki ,  Muneharu Gotoh

Inventor： Yutaka Mimino ,  Osamu Baba ,  Yoshio Aoki ,  Muneharu Gotoh

IPC: H01L21338

CPC classification number: H01L23/5222 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A high frequency semiconductor device includes a ground plate, an insulating layer, a power-supply conductor, an insulating interlayer, and a strip line as a line conductor. The power-supply conductor is disposed above the ground plate, with the insulating layer provided therebetween. The ground plate and the power-supply conductor have a capacitance formed therebetween. Thus, the line conductor regards the power-supply conductor as having a potential identical to that of the ground plate. This makes it possible to lay out the line conductor without considering the arrangement of the power-supply conductor. In other words, by two-dimensionally overlapping a microstrip line and a power-supply conductor in an MMIC, the degree of freedom in the device layout can be increased.

Abstract translation: 高频半导体器件包括接地板，绝缘层，电源导体，绝缘中间层和作为线导体的带状线。 电源导体设置在接地板的上方，绝缘层设置在它们之间。 接地板和电源导体之间形成有电容。 因此，线路导体将电源导体视为具有与接地板相同的电位。 这使得可以在不考虑电源导体的布置的情况下布线。 换句话说，通过在MMIC中二维地重叠微带线和电源导体，可以提高器件布局的自由度。

公开(公告)号：US06580166B2

公开(公告)日：2003-06-17

申请号：US10078450

申请日：2002-02-21

Applicant: Osamu Baba ,  Yutaka Mimino ,  Yoshio Aoki ,  Muneharu Gotoh

Inventor： Osamu Baba ,  Yutaka Mimino ,  Yoshio Aoki ,  Muneharu Gotoh

IPC: H01L2310

CPC classification number: H01L23/66 ,  H01L23/3677 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A high frequency semiconductor device includes semiconductor elements provided on a semiconductor substrate, a surface insulating layer for covering the semiconductor elements, at least one wiring layer which is provided above the surface insulating layer, with at least one insulating interlayer provided therebetween, and which combines with the ground potential to form transmission line, and at least one heat-radiating stud which is provided in at least one throughhole so as to penetrate said insulating interlayers and so as not to penetrate said surface insulating layer.