公开(公告)号：USRE35094E

公开(公告)日：1995-11-21

申请号：US974262

申请日：1992-11-10

Applicant: Tsung-Ching Wu ,  Geeng-Chuan Chern

Inventor： Tsung-Ching Wu ,  Geeng-Chuan Chern

IPC: H01L21/336 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/11524 ,  H01L29/66825

Abstract: An electrically programmable and electrically erasable MOS memory device having a floating gate which is separated from the semiconductor substrate by a thin oxide layer, the memory device also having an impurity implant in the substrate which extends under an edge of the floating gate beneath the thin oxide layer. In one embodiment the thin oxide layer underlies the entire floating gate while in another embodiment only a portion of a small thin side window extends under the floating gate's edge. Also disclosed is a fabrication process in which the one embodiment is formed by first forming the floating gate over the thin oxide layer and then implanting the impurity near an edge of the floating gate. Later steps with heating cause the implanted impurity to diffuse under the floating gate edge. An alternative process first forms a window in the gate oxide layer and implants the impurity through the window. The window is filled with a thin oxide layer and the floating gate is formed so that its edge lies over a portion of the window. Control gates, sources and drains are formed last.

公开(公告)号：US5081054A

公开(公告)日：1992-01-14

申请号：US652293

申请日：1991-02-05

Applicant: Tsung-Ching Wu ,  Geeng-Chuan Chern

Inventor： Tsung-Ching Wu ,  Geeng-Chuan Chern

IPC: H01L21/336 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/11524 ,  H01L29/66825

Abstract: An electrically programmable and electrically erasable MOS memory device having a floating gate which is separated from the semiconductor substrate by a thin oxide layer, the memory device also having an impurity implant in the substrate which extends under an edge of the floating gate beneath the thin oxide layer. In one embodiment the thin oxide layer underlies the entire floating gate while in another embodiment only a portion of a small thin side window extends under the floating gate's edge. Also disclosed is a fabrication process in which the one embodiment is formed by first forming the floating gate over the thin oxide layer and then implanting the impurity near an edge of the floating gate. Later steps with heating cause the implanted impurity to diffuse under the floating gate edge. An alternative process first forms a window in the gate oxide layer and implants the impurity through the window. The window is filled with a thin oxide layer and the floating gate is formed so that its edge lies over a portion of the window. Control gates, sources and drains are formed last.

Abstract translation: 一种电可编程和电可擦除的MOS存储器件，其具有通过薄氧化物层与半导体衬底分离的浮置栅极，该存储器件还具有在衬底中的杂质注入，其在薄氧化物下面的浮动栅极的边缘下方延伸 层。 在一个实施例中，薄氧化物层位于整个浮动栅极的下面，而在另一个实施例中，小的薄侧视窗的一部分仅在浮动栅极的边缘下方延伸。 还公开了一种制造工艺，其中通过首先在薄氧化物层上形成浮置栅极，然后将杂质在浮动栅极的边缘附近注入而形成。 稍后的加热步骤使注入的杂质在浮动栅极边缘下扩散。 一种替代方法首先在栅极氧化层中形成窗口，并通过窗口植入杂质。 窗口填充有薄的氧化物层，并且浮动栅极形成为使得其边缘位于窗口的一部分上方。 最后形成控制门，源和排水沟。

公开(公告)号：US5066992A

公开(公告)日：1991-11-19

申请号：US609017

申请日：1990-10-29

Applicant: Tsung-Ching Wu ,  Geeng-Chuan Chern

Inventor： Tsung-Ching Wu ,  Geeng-Chuan Chern

IPC: H01L27/115 ,  H01L29/788

CPC classification number: H01L29/7883 ,  H01L27/115

Abstract: An electrically programmable and electrically erasable MOS memory device having a floating gate which is separated from the semiconductor substrate by a thin oxide layer, the memory device also having an impurity implant in the substrate which extends under an edge of the floating gate beneath the thin oxide layer. In one embodiment the thin oxide layer underlies the entire floating gate while in another embodiment only a portion of a small thin side window extends under the floating gate's edge. Also disclosed is a fabrication process in which the one embodiment is formed by first forming the floating gate over the thin oxide layer and then implanting the impurity near an edge of the floating gate. Later steps with heating cause the implanted impurity to diffuse under the floating gate edge. An alternative process first forms a window in the gate oxide layer and implants the impurity through the window. The window is filled with a thin oxide layer and the floating gate is formed so that its edge lies over a portion of the window. Control gates, sources and drains are formed last.

Abstract translation: 一种电可编程和电可擦除的MOS存储器件，其具有通过薄氧化物层与半导体衬底分离的浮置栅极，该存储器件还具有在衬底中的杂质注入，其在薄氧化物下面的浮动栅极的边缘下方延伸 层。 在一个实施例中，薄氧化物层位于整个浮动栅极的下面，而在另一个实施例中，小的薄侧视窗的一部分仅在浮动栅极的边缘下方延伸。 还公开了一种制造工艺，其中通过首先在薄氧化物层上形成浮置栅极，然后将杂质在浮动栅极的边缘附近注入而形成。 稍后的加热步骤使注入的杂质在浮动栅极边缘下扩散。 一种替代方法首先在栅极氧化层中形成窗口，并通过窗口植入杂质。 窗口填充有薄的氧化物层，并且浮动栅极形成为使得其边缘位于窗口的一部分上方。 最后形成控制门，源和排水沟。

公开(公告)号：US4859619A

公开(公告)日：1989-08-22

申请号：US219924

申请日：1988-07-15

Applicant: Tsung-Ching Wu ,  Geeng-Chuan Chern ,  James C. Hu

Inventor： Tsung-Ching Wu ,  Geeng-Chuan Chern ,  James C. Hu

IPC: H01L21/762 ,  H01L21/8247

CPC classification number: H01L27/11526 ,  H01L21/76218 ,  H01L27/11546 ,  Y10S148/126

Abstract: A process of fabricating high performance EPROMs in which memory cell devices and high voltage circuit devices are formed in p-type tub regions of high threshold voltage. The tub regions are formed by implanting boron ions in photolithographically defined memory cell and high voltage device areas of a p-type wafer substrate, then subjecting the substrate to a high temperature drive-in. The N-channel isolation field is formed separately and has a lower threshold voltage than the tub regions. The isolation field is formed by implanting boron ions around all device areas, including low voltage device areas, using a nitride mask and a low implantation energy. The wafer is then subjected to an anneal step followed by a field oxidation step. The memory cell and other MOS devices are finally formed in the appropriate defined regions. Since the isolation field's threshold voltage can be adjusted separately from the tub regions, the threshold voltage of the field can be reduced making it possible to reduce the isolation spacing of low voltage devices, reduce parasitic capacitance and increase device speed.

Abstract translation: 制造高性能EPROM的方法，其中存储单元器件和高电压电路器件形成在高阈值电压的p型区域中。 通过在光刻定义的存储单元中注入硼离子和p型晶片衬底的高电压器件区域，然后使衬底经受高温驱入而形成桶区。 N沟道隔离场分开形成，并且具有比桶区域更低的阈值电压。 通过使用氮化物掩模和低注入能量将硼离子注入所有器件区域（包括低电压器件区域）来形成隔离场。 然后对晶片进行退火步骤，然后进行场氧化步骤。 存储单元和其他MOS器件最终形成在适当的限定区域中。 由于隔离场的阈值电压可以与桶区域分开调整，所以可以减小场的阈值电压，从而可以降低低压器件的隔离间隔，降低寄生电容并提高器件速度。

公开(公告)号：US06743703B2

公开(公告)日：2004-06-01

申请号：US10238104

申请日：2002-09-09

Applicant: Vladimir Rodov ,  Paul Chang ,  Jianren Bao ,  Wayne Y. W. Hsueh ,  Arthur Ching-Lang Chiang ,  Geeng-Chuan Chern

Inventor： Vladimir Rodov ,  Paul Chang ,  Jianren Bao ,  Wayne Y. W. Hsueh ,  Arthur Ching-Lang Chiang ,  Geeng-Chuan Chern

IPC: H01L2974

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L27/0727 ,  H01L27/0814 ,  H01L27/095 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/781 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A two-terminal power diode has improved reverse bias breakdown voltage and on resistance includes a semiconductor body having two opposing surfaces and a superjunction structure therebetween, the superjunction structure including a plurality of alternating P and N doped regions aligned generally perpendicular to the two surfaces. The P and N doped regions can be parallel stripes or a mesh with each region being surrounded by doped material of opposite conductivity type. A diode junction associated with one surface can be an anode region with a gate controlled channel region connecting the anode region to the superjunction structure. Alternatively, the diode junction can comprise a metal forming a Schottky junction with the one surface. The superjunction structure is within the cathode and spaced from the anode. The spacing can be varied during device fabrication.

Abstract translation: 双端功率二极管具有改进的反向偏压击穿电压，并且导通电阻包括具有两个相对表面的半导体本体和它们之间的超结结构，所述超结结构包括多个交替的P和N掺杂区域，其大致垂直于两个表面排列。 P和N掺杂区域可以是平行条纹或网状物，每个区域被相反导电类型的掺杂材料包围。 与一个表面相关联的二极管结可以是具有将阳极区域连接到超结构结构的栅极控制沟道区域的阳极区域。 或者，二极管结可以包括与该表面形成肖特基结的金属。 超结构在阴极内并与阳极间隔开。 间隔可以在器件制造过程中变化。

公开(公告)号：US06537860B2

公开(公告)日：2003-03-25

申请号：US09739732

申请日：2000-12-18

Applicant: Hidenori Akiyama ,  Paul Chang ,  Geeng-Chuan Chern ,  Wayne Y. W. Hsueh ,  Haru Ohkawa ,  Yasuo Ohtsuki ,  Vladimir Rodov

Inventor： Hidenori Akiyama ,  Paul Chang ,  Geeng-Chuan Chern ,  Wayne Y. W. Hsueh ,  Haru Ohkawa ,  Yasuo Ohtsuki ,  Vladimir Rodov

IPC: H01L21332

CPC classification number: H01L29/6609 ,  H01L29/0619 ,  H01L29/7391 ,  H01L29/861

Abstract: A method for manufacturing a discrete power rectifier device having a VLSI multi-cell design employs a two spacer approach to defining a P/N junction profile having good breakdown voltage characteristics. The method provides highly repeatable device characteristics at reduced cost. The active channel regions of the device are also defined using the same two spacers. The method is a self-aligned process and channel dimensions and doping characteristics may be precisely controlled despite inevitable process variations in spacer formation. Only two masking steps are required, and additional spacers for defining the body region profile can be avoided, reducing processing costs.

公开(公告)号：US06420225B1

公开(公告)日：2002-07-16

申请号：US09805815

申请日：2001-03-13

Applicant: Paul Chang ,  Vladimir Rodov ,  Geeng-Chuan Chern ,  Charles Lin ,  Ching-Lang Chiang

Inventor： Paul Chang ,  Vladimir Rodov ,  Geeng-Chuan Chern ,  Charles Lin ,  Ching-Lang Chiang

IPC: H01L218234

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L27/0727 ,  H01L27/0814 ,  H01L27/095 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66356 ,  H01L29/66712 ,  H01L29/781 ,  H01L29/861

Abstract: A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate.

Abstract translation: 一种垂直半导体整流器件包括第一导电类型的半导体衬底，并且具有绝缘地形成在第一主表面上的多个栅极和在第一导电类型的第一导电类型的表面区域中形成的多个第一导电类型的源极/漏极区域 主要表面毗邻门。 第二导电类型的多个通道各自邻接源/漏区并在栅极下方延伸。

公开(公告)号：US20110223729A1

公开(公告)日：2011-09-15

申请号：US13108630

申请日：2011-05-16

Applicant: Paul Chang ,  Geeng-Chuan Chern ,  Prognyan Ghosh ,  Wayne Y.W. Hsueh ,  Vladmir Rodov

Inventor： Paul Chang ,  Geeng-Chuan Chern ,  Prognyan Ghosh ,  Wayne Y.W. Hsueh ,  Vladmir Rodov

IPC: H01L21/8234

CPC classification number: H01L27/0629 ,  H01L29/0692 ,  H01L29/78 ,  H01L29/861

Abstract: A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.

Abstract translation: 一种制造包括功率二极管的半导体集成电路的方法包括提供第一导电类型的半导体衬底，在衬底的第一区域中制造诸如CMOS晶体管电路的集成电路，并且在第二区域中制造功率二极管 半导体衬底。 介电材料形成在第一区域和第二区域之间，从而在第一区域中的集成电路与第二区域中的功率二极管之间提供电隔离。 功率二极管可以包括由二极管的一个电极连接在一起的多个MOS源极/漏极元件和相关联的栅极元件，并且第二区域中的半导体层可以用作功率二极管的另一个源极/漏极。

公开(公告)号：US07964933B2

公开(公告)日：2011-06-21

申请号：US11821234

申请日：2007-06-22

Applicant: Paul Chang ,  Geeng-Chuan Chern ,  Prognyan Ghosh ,  Wayne Y. W. Hsueh ,  Vladimir Rodov

Inventor： Paul Chang ,  Geeng-Chuan Chern ,  Prognyan Ghosh ,  Wayne Y. W. Hsueh ,  Vladimir Rodov

IPC: H01L21/76

CPC classification number: H01L27/0629 ,  H01L29/0692 ,  H01L29/78 ,  H01L29/861

Abstract: A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.

Abstract translation: 一种制造包括功率二极管的半导体集成电路的方法包括提供第一导电类型的半导体衬底，在衬底的第一区域中制造诸如CMOS晶体管电路的集成电路，并且在第二区域中制造功率二极管 半导体衬底。 介电材料形成在第一区域和第二区域之间，从而在第一区域中的集成电路与第二区域中的功率二极管之间提供电隔离。 功率二极管可以包括由二极管的一个电极连接在一起的多个MOS源极/漏极元件和相关联的栅极元件，并且第二区域中的半导体层可以用作功率二极管的另一个源极/漏极。

公开(公告)号：US07084453B2

公开(公告)日：2006-08-01

申请号：US10850300

申请日：2004-05-19

Applicant: Geeng-Chuan Chern ,  Amitay Levi ,  Dana Lee

Inventor： Geeng-Chuan Chern ,  Amitay Levi ,  Dana Lee

IPC: H01L21/8238 ,  H01L21/336 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11526 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/11539 ,  Y10S438/981

Abstract: A semiconductor memory device and method for making the same, where a memory cell and high voltage MOS transistor are formed on the same substrate. An insulating layer is formed having a first portion that insulates the control and floating gates of the memory cell from each other, and a second portion that insulates the poly gate from the substrate in the MOS transistor. The insulating layer is formed so that its first portion has a smaller thickness than that of its second portion.