公开(公告)号：US20050030055A1

公开(公告)日：2005-02-10

申请号：US10634484

申请日：2003-08-05

申请人： Tu-Anh Tran ,  Richard Eguchi ,  Peter Harper ,  Chu-Chung Lee ,  William Williams ,  Lois Yong

发明人： Tu-Anh Tran ,  Richard Eguchi ,  Peter Harper ,  Chu-Chung Lee ,  William Williams ,  Lois Yong

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3187 ,  G11C29/48 ,  G01R31/02

CPC分类号： G11C29/1201 ,  G01R31/2884 ,  G01R31/31715 ,  G01R31/3187 ,  G11C29/48 ,  H01L2224/05554

摘要： A semiconductor device has a large number of bond pads on the periphery for wirebonding. The semiconductor device has a module as well as other circuitry, but the module takes significantly longer to test than the other circuitry. A relatively small number of the bond pads, the module bond pads, are required for the module testing due, at least in part, to the semiconductor device having a built-in self-test (BIST) circuitry. The functionality of these module bond pads is duplicated on the top surface of and in the interior of the semiconductor device with module test pads that are significantly larger than the bond pads on the periphery. Having large pads for testing allows longer probe needles, thus increasing parallel testing capability. Duplicating the functionality is achieved through a test pad interface so that the module bond pads and the module test pads do not have to be shorted together.

公开(公告)号：US20110107160A1

公开(公告)日：2011-05-05

申请号：US12608476

申请日：2009-10-29

申请人： Richard Eguchi ,  Thomas S. Harp ,  Thomas Jew

发明人： Richard Eguchi ,  Thomas S. Harp ,  Thomas Jew

IPC分类号： G11C29/04 ,  G06F11/00 ,  G06F11/22

CPC分类号： G06F11/1008 ,  G06F11/004 ,  G11C2029/0411

摘要： A technique for detecting an imminent read failure in a memory array includes determining a first incident count for a memory array that does not exhibit an uncorrectable error correcting code (ECC) read during an array integrity check. In this case, the first incident count corresponds to an initial number of ECC corrections that are performed when the array integrity check of the memory array initially fails. The technique also includes determining a current count for the memory array when the memory array does not exhibit an uncorrectable ECC read during subsequent array integrity checks. In this case, the current count corresponds to a subsequent number of error correcting code (ECC) corrections required during the subsequent array integrity checks. An indication of an imminent read failure for the memory array is provided when the current count exceeds the first incident count by a predetermined amount.

摘要翻译： 一种用于检测存储器阵列中即将发生的读取故障的技术包括确定在阵列完整性检查期间不显示读取的不可校正纠错码（ECC）的存储器阵列的第一事件计数。 在这种情况下，第一事件计数对应于当存储器阵列的阵列完整性检查最初失败时执行的ECC校正的初始数量。 该技术还包括当在随后的阵列完整性检查期间存储器阵列不呈现不可校正的ECC读取时确定存储器阵列的当前计数。 在这种情况下，当前计数对应于随后的阵列完整性检查期间所需的纠错码（ECC）修正的随后数量。 当当前计数超过第一事件计数预定量时，提供存储器阵列即将发生读取故障的指示。

公开(公告)号：US20070204098A1

公开(公告)日：2007-08-30

申请号：US11364129

申请日：2006-02-28

申请人： Richard Eguchi ,  Jon Choy

发明人： Richard Eguchi ,  Jon Choy

IPC分类号： G06F12/00

CPC分类号： G06F12/0246

摘要： A non-volatile memory can have multiple blocks erased in parallel for a relatively few number of erase operations. This saves time for the user in the set-up of the memory because the erase operation is relatively slow. Problems with parallel erase relate to different blocks having different program/erase histories with the result that the blocks with different histories erase differently. Thus, after a predetermined number of erase cycles are performed, the ability to parallel erase is prevented. This is achieved by allowing parallel erasing operations until the predetermined number of erase operations have been counted. After that predetermined number has been reached, a parallel erase mode disable signal is generated to prevent further parallel erase cycles. The count and the predetermined number are maintained in a small block of the non-volatile memory that is inaccessible to the user.

摘要翻译： 非易失性存储器可以具有并行擦除多个块，用于相对较少数量的擦除操作。 这样可以节省用户设置存储器的时间，因为擦除操作相对较慢。 并行擦除的问题涉及具有不同程序/擦除历史的不同块，结果是具有不同历史的块被擦除不同。 因此，在执行预定数量的擦除周期之后，防止并行擦除的能力。 这通过允许并行擦除操作直到预定数量的擦除操作被计数来实现。 在达到预定数量之后，产生并行擦除模式禁止信号，以防止进一步的并行擦除周期。 计数和预定数量被保持在用户无法访问的非易失性存储器的小块中。

公开(公告)号：US20110107161A1

公开(公告)日：2011-05-05

申请号：US12608405

申请日：2009-10-29

申请人： Richard Eguchi ,  Thomas S. Harp ,  Thomas Jew ,  Peter J. Kuhn ,  Timothy J. Strauss

发明人： Richard Eguchi ,  Thomas S. Harp ,  Thomas Jew ,  Peter J. Kuhn ,  Timothy J. Strauss

IPC分类号： G11C29/04 ,  G06F11/22

CPC分类号： G11C29/50004 ,  G11C16/26 ,  G11C29/42 ,  G11C2029/0411

摘要： A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level.

摘要翻译： 用于检测存储器阵列中即将发生的读取故障的技术包括确定在正常读取验证电压电平下的初始阵列完整性检查期间不显示不能校正的纠错码（ECC）的存储器阵列是否显示出不可校正的ECC 在随后的阵列完整性检查期间读取读取验证电压电平。 当在后续阵列完整性检查期间存储器阵列呈现不可校正的ECC读取时，该技术还包括提供针对存储器阵列的迫在眉睫的读取失败的指示。 在这种情况下，余量读取验证电压电平与正常读取验证电压电平不同。