公开(公告)号：US20050030055A1

公开(公告)日：2005-02-10

申请号：US10634484

申请日：2003-08-05

申请人： Tu-Anh Tran ,  Richard Eguchi ,  Peter Harper ,  Chu-Chung Lee ,  William Williams ,  Lois Yong

发明人： Tu-Anh Tran ,  Richard Eguchi ,  Peter Harper ,  Chu-Chung Lee ,  William Williams ,  Lois Yong

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3187 ,  G11C29/48 ,  G01R31/02

CPC分类号： G11C29/1201 ,  G01R31/2884 ,  G01R31/31715 ,  G01R31/3187 ,  G11C29/48 ,  H01L2224/05554

摘要： A semiconductor device has a large number of bond pads on the periphery for wirebonding. The semiconductor device has a module as well as other circuitry, but the module takes significantly longer to test than the other circuitry. A relatively small number of the bond pads, the module bond pads, are required for the module testing due, at least in part, to the semiconductor device having a built-in self-test (BIST) circuitry. The functionality of these module bond pads is duplicated on the top surface of and in the interior of the semiconductor device with module test pads that are significantly larger than the bond pads on the periphery. Having large pads for testing allows longer probe needles, thus increasing parallel testing capability. Duplicating the functionality is achieved through a test pad interface so that the module bond pads and the module test pads do not have to be shorted together.

公开(公告)号：US06937047B2

公开(公告)日：2005-08-30

申请号：US10634484

申请日：2003-08-05

申请人： Tu-Anh Tran ,  Richard K. Eguchi ,  Peter R. Harper ,  Chu-Chung Lee ,  William M. Williams ,  Lois Yong

发明人： Tu-Anh Tran ,  Richard K. Eguchi ,  Peter R. Harper ,  Chu-Chung Lee ,  William M. Williams ,  Lois Yong

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3187 ,  G11C29/48 ,  G01R31/02

CPC分类号： G11C29/1201 ,  G01R31/2884 ,  G01R31/31715 ,  G01R31/3187 ,  G11C29/48 ,  H01L2224/05554

摘要： A semiconductor device has a large number of bond pads on the periphery for wirebonding. The semiconductor device has a module as well as other circuitry, but the module takes significantly longer to test than the other circuitry. A relatively small number of the bond pads, the module bond pads, are required for the module testing due, at least in part, to the semiconductor device having a built-in self-test (BIST) circuitry. The functionality of these module bond pads is duplicated on the top surface of and in the interior of the semiconductor device with module test pads that are significantly larger than the bond pads on the periphery. Having large pads for testing allows longer probe needles, thus increasing parallel testing capability. Duplicating the functionality is achieved through a test pad interface so that the module bond pads and the module test pads do not have to be shorted together.

摘要翻译： 半导体器件在外围具有大量用于引线键合的接合焊盘。 该半导体器件具有模块以及其他电路，但该模块比其他电路需要更长的测试时间。 由于至少部分地由具有内置自检（BIST）电路的半导体器件，模块测试需要相对较少数量的接合焊盘（模块接合焊盘）。 这些模块接合焊盘的功能在半导体器件的顶表面和内部复制，模块测试焊盘明显大于外围的焊盘。 具有大的测试垫可以延长探针，从而提高并行测试能力。 通过测试接口接口实现复制功能，使得模块接合焊盘和模块测试焊盘不必一起短路。

公开(公告)号：US20060237850A1

公开(公告)日：2006-10-26

申请号：US11110283

申请日：2005-04-20

申请人： Yuan Yuan ,  Kevin Hess ,  Chu-Chung Lee ,  Tu-Anh Tran ,  Alan Woosley ,  Donna Woosley

发明人： Yuan Yuan ,  Kevin Hess ,  Chu-Chung Lee ,  Tu-Anh Tran ,  Alan Woosley ,  Donna Woosley

IPC分类号： H01L23/48

CPC分类号： H01L23/3185 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit has a semiconductor substrate and an interconnect layer that mechanically relatively weak and susceptible to cracks and delamination. In the formation of the integrated circuit from a semiconductor wafer, a cut is made through the interconnect layer to form an edge of the interconnect layer. This cut may continue completely through the wafer thickness or stop short of doing so. In either case, after cutting through the interconnect layer, a reconditioning layer is formed on the edge of the interconnect layer. This reconditioning layer seals the existing cracks and delaminations and inhibits the further delamination or cracking of the interconnect layer. The sealing layer may be formed, for example, before the cut through the wafer, after the cut through the wafer but before any packaging, or after performing wirebonding between the interconnect layer and an integrated circuit package.

摘要翻译： 集成电路具有机械相对较弱并易于产生裂纹和分层的半导体衬底和互连层。 在从半导体晶片形成集成电路的过程中，通过互连层进行切割以形成互连层的边缘。 该切割可以完全延续晶片厚度，或者停止这样做。 在任一情况下，在切穿互连层之后，在互连层的边缘上形成再生层。 该修复层密封现有的裂纹和分层，并且抑制互连层的进一步分层或破裂。 密封层可以例如在经过晶片切割之后，经过晶片切割之后，但在任何包装之前，或者在互连层和集成电路封装之间进行引线键合之后形成。

公开(公告)号：US20070087067A1

公开(公告)日：2007-04-19

申请号：US11252409

申请日：2005-10-18

申请人： Yuan Yuan ,  Chu-Chung Lee ,  Tu-Anh Tran ,  Paul Winebarger

发明人： Yuan Yuan ,  Chu-Chung Lee ,  Tu-Anh Tran ,  Paul Winebarger

IPC分类号： B23B19/00

CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A die (10) for an integrated circuit comprising an active area (22) is provided. The die (10) may further comprise a first ring (12) in a peripheral region of the die (10) at least partially surrounding the active area (22), wherein the first ring (12) may comprise a plurality of polygon shaped cells (32, 36). The die (10) may further comprise a second ring (14) surrounding the first ring (12), wherein the second ring (14) may comprise a plurality of polygon shaped cells (32, 36).

摘要翻译： 提供了一种用于包括有源区域（22）的集成电路的管芯（10）。 模具（10）还可以包括至少部分地围绕有源区域（22）的模具（10）的周边区域中的第一环（12），其中第一环（12）可以包括多个多边形形状的单元 （32,36）。 模具（10）还可以包括围绕第一环（12）的第二环（14），其中第二环（14）可以包括多个多边形形状的单元（32,36）。

公开(公告)号：US09437574B2

公开(公告)日：2016-09-06

申请号：US14042662

申请日：2013-09-30

申请人： Tu-Anh N. Tran ,  Chu-Chung Lee

发明人： Tu-Anh N. Tran ,  Chu-Chung Lee

IPC分类号： H05K1/11 ,  H05K1/09 ,  H01L23/00

CPC分类号： H01L24/85 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/04042 ,  H01L2224/05017 ,  H01L2224/05085 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45644 ,  H01L2224/45664 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48824 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/85207 ,  H01L2224/8581 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  Y10T29/49124 ,  H01L2924/01004 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/01012 ,  H01L2924/01016 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electronic component package includes a substrate and dielectric structure. The dielectric structure includes a top surface having a protrusion portion and a lower portion. The protrusion portion is located at first height that is greater than a second height of the lower portion. A conductive bond pad is located over the dielectric structure. A ball bond electrically couples the bond pad and a bond wire. An intermetallic compound located between the ball bond and bond pad is formed of material of the ball bond and bond pad and electrically couples the bond pad to the ball bond. A portion of the bond pad is vertically located between a portion of the lower portion of the top surface of the dielectric structure and the intermetallic compound. No portion of the bond pad is vertically located between at least a portion of the protrusion portion and the intermetallic compound.

摘要翻译： 电子部件封装包括基板和电介质结构。 电介质结构包括具有突出部分和下部分的顶表面。 突出部位于大于下部的第二高度的第一高度。 导电接合焊盘位于电介质结构之上。 球接合电耦合接合焊盘和接合线。 位于球焊接和焊盘之间的金属间化合物由球焊和焊盘的材料形成，并将焊接焊盘电连接到球焊上。 接合焊盘的一部分垂直地位于电介质结构的顶表面的下部的一部分和金属间化合物之间。 接合焊盘的没有部分垂直地位于突出部分的至少一部分和金属间化合物之间。

公开(公告)号：US09324675B2

公开(公告)日：2016-04-26

申请号：US14262381

申请日：2014-04-25

申请人： Burton J. Carpenter ,  Chu-Chung Lee ,  Tu-Anh N. Tran

发明人： Burton J. Carpenter ,  Chu-Chung Lee ,  Tu-Anh N. Tran

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC分类号： H01L24/49 ,  H01L24/05 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/431 ,  H01L2224/432 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45644 ,  H01L2224/45664 ,  H01L2224/45687 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4845 ,  H01L2224/48451 ,  H01L2224/48456 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/49171 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85931 ,  H01L2224/85939 ,  H01L2224/85947 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/013 ,  H01L2924/01047 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/00013 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor structure includes a bond pad and a wire bond coupled to the bond pad. The wire bond includes a bond in contact with the bond pad. The wire bond includes a coating on a surface of the wire bond, and a first exposed portion of the wire bond in a selected location. The wire bond is devoid of the coating over the selected location of the wire bond, and an area of the first exposed portion is at least one square micron.

摘要翻译： 半导体结构包括接合焊盘和耦合到接合焊盘的引线键合。 引线键合包括与接合焊盘接触的键。 引线接合包括在引线键合的表面上的涂层，以及在选定位置的引线键合的第一暴露部分。 引线接合在引线键合的选定位置上没有涂层，并且第一暴露部分的面积为至少一平方微米。

公开(公告)号：US07632715B2

公开(公告)日：2009-12-15

申请号：US11620074

申请日：2007-01-05

申请人： Kevin J. Hess ,  Chu-Chung Lee ,  Robert J. Wenzel

发明人： Kevin J. Hess ,  Chu-Chung Lee ,  Robert J. Wenzel

IPC分类号： H01L21/00

CPC分类号： H01L23/295 ,  H01L21/561 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/15311

摘要： A method of packaging a semiconductor includes providing a support structure. An adhesive layer is formed overlying the support structure and is in contact with the support structure. A plurality of semiconductor die is placed on the adhesive layer. The semiconductor die are laterally separated from each other and have electrical contacts that are in contact with the adhesive layer. A layer of encapsulating material is formed overlying and between the plurality of semiconductor die and has a distribution of filler material. A concentration of the filler material is increased in all areas laterally adjacent each of the plurality of semiconductor die.

摘要翻译： 包装半导体的方法包括提供支撑结构。 粘合层形成在支撑结构上方并与支撑结构接触。 多个半导体管芯被放置在粘合剂层上。 半导体管芯相互横向分离并具有与粘合剂层接触的电接触。 一层封装材料形成在多个半导体管芯之间并且在多个半导体管芯之间并且具有填充材料的分布。 填充材料的浓度在与多个半导体管芯中的每一个横向相邻的所有区域中增加。

公开(公告)号：US07550318B2

公开(公告)日：2009-06-23

申请号：US11502679

申请日：2006-08-11

申请人： Kevin J. Hess ,  Chu-Chung Lee ,  James W. Miller

发明人： Kevin J. Hess ,  Chu-Chung Lee ,  James W. Miller

IPC分类号： H01L21/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5389 ,  H01L23/49517 ,  H01L24/24 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/85 ,  H01L24/91 ,  H01L2224/05553 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/82007 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method is provided for forming peripheral contacts between a die and a substrate. In accordance with the method, a die (305) is provided which has first and second opposing major surfaces, wherein the first major surface is attached to a substrate (303) having a first group (323) of contact pads disposed thereon, and wherein the second major surface has a second group (311) of contact pads disposed thereon. An electrically conductive pathway (326) is formed between the first and second groups of contacts with an electrically conductive polymeric composition.

摘要翻译： 提供一种用于在管芯和衬底之间形成周边接触的方法。 根据该方法，提供具有第一和第二相对主表面的模具（305），其中第一主表面附接到具有设置在其上的第一组（323）接触垫的基板（303），并且其中 第二主表面具有设置在其上的第二接触焊盘组（311）。 在第一和第二组触点之间用导电聚合物组合物形成导电通路（326）。

公开(公告)号：US20050189643A1

公开(公告)日：2005-09-01

申请号：US10787288

申请日：2004-02-26

申请人： Yaping Zhou ,  Chu-Chung Lee

发明人： Yaping Zhou ,  Chu-Chung Lee

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L23/552

CPC分类号： H01L24/85 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45166 ,  H01L2224/45184 ,  H01L2224/45565 ,  H01L2224/45684 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00

摘要： A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.

摘要翻译： 半导体封装使用各种形式的导电迹线，其通过接合线连接到管芯接合焊盘。 在一种形式中，相邻的接合线有意地绕其中点越过，以减少导体的自感并且使自感最小化。 在另一种形式中，与具有中间的，不相关的键合焊盘的接合焊盘相关联的接合线交叉。 另外，导电迹线被分成单独的部分，并通过交叉的跳线或接合线电连接。 可以为每个迹线形成任何数量的分开的部分，但是偶数是优选的。 在另一种形式中，一条迹线是连续的，并将第二条迹线划分成两个或多个部分。 多个部分通过上覆的接合线连接。 可以使用绝缘或非绝缘的接合线。

公开(公告)号：US06933614B2

公开(公告)日：2005-08-23

申请号：US10662541

申请日：2003-09-15

申请人： Chu-Chung Lee ,  Fuaida Harun ,  Kevin J. Hess ,  Lan Chu Tan ,  Cheng Choi Yong

发明人： Chu-Chung Lee ,  Fuaida Harun ,  Kevin J. Hess ,  Lan Chu Tan ,  Cheng Choi Yong

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/48

CPC分类号： H01L24/85 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48647 ,  H01L2224/48747 ,  H01L2224/48847 ,  H01L2224/85013 ,  H01L2224/85207 ,  H01L2224/85375 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2224/78 ,  H01L2924/00

摘要： An integrated circuit die (10) has a copper contact (16, 18), which, upon exposure to the ambient air, forms a native copper oxide. An organic material is applied to the copper contact which reacts with the native copper oxide to form an organic coating (12, 14) on the copper contact in order to prevent further copper oxidation. In this manner, further processing at higher temperatures, such as those greater than 100 degrees Celsius, is not inhibited by excessive copper oxidation. For example, due to the organic coating, the high temperature of the wire bond process does not result in excessive oxidation which would prevent reliable wire bonding. Thus, the formation of the organic coating allows for a reliable and thermal resistance wire bond (32, 34). Alternatively, the organic coating can be formed over exposed copper at any time during the formation of the integrated circuit die to prevent or limit the formation of copper oxidation.

摘要翻译： 集成电路管芯（10）具有铜接触（16,18），其在暴露于环境空气时形成天然铜氧化物。 将有机材料施加到与天然氧化铜反应的铜接触处，以在铜接触上形成有机涂层（12,14），以防止进一步的铜氧化。 以这种方式，在较高温度（例如大于100摄氏度的温度）下的进一步处理不会被过度的铜氧化所阻碍。 例如，由于有机涂层，引线键合过程的高温不会导致过度的氧化，这将阻止可靠的引线接合。 因此，有机涂层的形成允许可靠和耐热的引线键合（32,34）。 或者，可以在形成集成电路管芯期间的任何时间在暴露的铜上形成有机涂层，以防止或限制铜氧化的形成。