公开(公告)号：US12249649B2

公开(公告)日：2025-03-11

申请号：US17207751

申请日：2021-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Han Wu ,  Hsin-Yu Chen ,  Chun-Hao Lin ,  Shou-Wei Hsieh ,  Chih-Ming Su ,  Yi-Ren Chen ,  Yuan-Ting Chuang

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/417

Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.

公开(公告)号：US10991824B2

公开(公告)日：2021-04-27

申请号：US16252715

申请日：2019-01-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Han Wu ,  Hsin-Yu Chen ,  Chun-Hao Lin ,  Shou-Wei Hsieh ,  Chih-Ming Su ,  Yi-Ren Chen ,  Yuan-Ting Chuang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/417

Abstract: A semiconductor device includes: a fin-shaped structure on the substrate; a shallow trench isolation (STI) around the fin-shaped structure; a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure; a second gate structure on the STI; and a third gate structure on the SDB structure, wherein a width of the third gate structure is greater than a width of the second gate structure.

公开(公告)号：US20170222026A1

公开(公告)日：2017-08-03

申请号：US15014037

申请日：2016-02-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ren Chen ,  Shou-Wei Hsieh ,  Hsin-Yu Chen ,  Chun-Hao Lin ,  Yuan-Ting Chuang ,  Che-Hung Liu

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L29/66795 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/31111 ,  H01L29/66545 ,  H01L29/7847

Abstract: The present invention provides a method of fabricating a fin field effect transistor (finFET), comprising: firstly, an interfacial layer is formed on a fin structure, next, a high-k dielectric layer is formed on the interfacial layer; afterwards, a stress film is formed on the high-k dielectric layer, an annealing process is then performed to the stress film, and an etching process is performed to remove the stress film.

公开(公告)号：US20250063776A1

公开(公告)日：2025-02-20

申请号：US18373953

申请日：2023-09-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Chun-Hao Lin ,  Yuan-Ting Chuang ,  Shou-Wei Hsieh

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a first electrically conductive structure. The semiconductor substrate has a planar device region and a fin device region. The semiconductor substrate includes a mesa structure disposed in the planar device region and fin-shaped structures disposed in the fin device region. The isolation structure is disposed on the semiconductor substrate and includes a first portion which is disposed on the planar device region and covers a sidewall of the mesa structure, and the isolation structure further includes a second portion which is disposed on the fin device region and located between the fin-shaped structures. The first electrically conductive structure is disposed on the planar device region. The first electrically conductive structure is partly disposed above the mesa structure in a vertical direction and partly disposed above the first portion of the isolation structure in the vertical direction.

公开(公告)号：US20240162220A1

公开(公告)日：2024-05-16

申请号：US18078064

申请日：2022-12-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Chun-Hao Lin ,  Yuan-Ting Chuang ,  Shou-Wei Hsieh

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/823475 ,  H01L28/75 ,  H01L28/87 ,  H01L28/91

Abstract: A capacitor on a fin structure includes a fin structure. A dielectric layer covers the fin structure. A first electrode extension is embedded within the fin structure. A first electrode penetrates the dielectric layer and contacts the first electrode extension. A second electrode and a capacitor dielectric layer are disposed within the dielectric layer. The capacitor dielectric layer surrounds the second electrode, and the capacitor dielectric layer is between the second electrode and the first electrode extension.

公开(公告)号：US20210210628A1

公开(公告)日：2021-07-08

申请号：US17207751

申请日：2021-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Han Wu ,  Hsin-Yu Chen ,  Chun-Hao Lin ,  Shou-Wei Hsieh ,  Chih-Ming Su ,  Yi-Ren Chen ,  Yuan-Ting Chuang

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/417

Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.