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公开(公告)号:US20160276434A1
公开(公告)日:2016-09-22
申请号:US15166271
申请日:2016-05-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chun Jen Chen , Bin-Siang Tsai , Tsai-Yu Wen , Yu Shu Lin , Chin-Sheng Yang
IPC: H01L29/06 , H01L29/423 , H01L29/78 , H01L29/41
CPC classification number: H01L29/0676 , B82Y10/00 , B82Y40/00 , H01L21/02236 , H01L21/02255 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02535 , H01L21/02587 , H01L21/02603 , H01L21/0262 , H01L21/02639 , H01L21/02664 , H01L21/76224 , H01L29/0673 , H01L29/068 , H01L29/16 , H01L29/165 , H01L29/413 , H01L29/42392 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L2029/7858
Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a first nanowire disposed over the substrate; a second nanowire disposed over the substrate; a first pad formed at first ends of the first and second nanowires, a second pad formed at second ends of the first and second nanowires, wherein the pads comprise different materials than the nanowires; and a gate surrounding at least a portion of each of the first and second nanowires.
Abstract translation: 提供半导体器件。 半导体器件包括衬底; 设置在衬底上的第一纳米线; 设置在衬底上的第二纳米线; 形成在第一和第二纳米线的第一端处的第一焊盘,形成在第一和第二纳米线的第二端处的第二焊盘,其中焊盘包括与纳米线不同的材料; 以及围绕第一和第二纳米线的每一个的至少一部分的栅极。
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公开(公告)号:US09653549B2
公开(公告)日:2017-05-16
申请号:US15166271
申请日:2016-05-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chun Jen Chen , Bin-Siang Tsai , Tsai-Yu Wen , Yu Shu Lin , Chin-Sheng Yang
IPC: H01L29/66 , H01L29/06 , H01L21/02 , H01L29/423 , H01L29/78 , H01L29/165 , H01L29/775 , H01L29/41
CPC classification number: H01L29/0676 , B82Y10/00 , B82Y40/00 , H01L21/02236 , H01L21/02255 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02535 , H01L21/02587 , H01L21/02603 , H01L21/0262 , H01L21/02639 , H01L21/02664 , H01L21/76224 , H01L29/0673 , H01L29/068 , H01L29/16 , H01L29/165 , H01L29/413 , H01L29/42392 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L2029/7858
Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a first nanowire disposed over the substrate; a second nanowire disposed over the substrate; a first pad formed at first ends of the first and second nanowires, a second pad formed at second ends of the first and second nanowires, wherein the pads comprise different materials than the nanowires; and a gate surrounding at least a portion of each of the first and second nanowires.
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