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    Hierarchical wafer yield prediction method and hierarchical lifetime prediction method
    1.
    发明授权
    Hierarchical wafer yield prediction method and hierarchical lifetime prediction method 有权
    分层晶圆产量预测方法和分层寿命预测方法

    公开(公告)号：US09129076B2

    公开(公告)日：2015-09-08

    申请号：US14099997

    申请日：2013-12-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Ming Hou ,  Ji-Fu Kung

    IPC: G06F17/50 ,  H01L21/66

    CPC classification number: G01R31/2642 ,  G06F17/50 ,  H01L22/14 ,  H01L22/20

    Abstract: For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield domain for wafer yield prediction and a lifetime domain for a wafer lifetime prediction, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised.

    Abstract translation: 为了改善晶片制造，通过确定晶片产量预测的屈服域的系数和晶片寿命预测的寿命域，整合域，电/布局域，计量/缺陷域和 机器传感器域以分层方式。 借助于层次确定的系数，可以减少预测中的噪声，从而可以提高晶片的产量或寿命的预测结果的精度。

    Layout correcting method and layout correcting system
    2.
    发明授权
    Layout correcting method and layout correcting system 有权
    布局校正方法和布局校正系统

    公开(公告)号：US08930865B1

    公开(公告)日：2015-01-06

    申请号：US14150046

    申请日：2014-01-08

    Applicant: United Microelectronics Corp.

    Inventor： Hsin-Ming Hou ,  Ji-Fu Kung

    IPC: G06F17/50

    CPC classification number: G06F17/5081

    Abstract: A layout correcting method and a layout correcting system are provided. The layout correcting method includes the following steps. An integrated circuit design layout is provided. A plurality of performance parameters of the integrated circuit design layout are analyzed. A plurality of devices under test is selected according to the performance parameters. A computer simulating process is performed on the devices under test and a direct probing process is performed on the devices under test. The direct probing process is an on-chip test for comparing each device under test and an environment condition thereof by a Boolean algebra algorithm. A plurality of differences between the results of the computer simulating process and the direct probing process is analyzed. The integrated circuit design layout is corrected according to differences between the results of the computer simulating process and the direct probing process.

    Abstract translation: 提供了布局校正方法和布局校正系统。 布局校正方法包括以下步骤。 提供集成电路设计布局。 分析了集成电路设计布局的多个性能参数。 根据性能参数选择被测试的多个设备。 对被测设备进行计算机模拟处理，并对被测设备进行直接探测过程。 直接探测过程是一种片上测试，用于通过布尔代数算法比较每个待测器件及其环境条件。 分析了计算机模拟过程的结果与直接探测过程之间的多个差异。 根据计算机模拟过程的结果与直接探测过程的不同，校正了集成电路设计布局。

    INSULATED GATE BIPOLAR TRANSISTOR
    3.
    发明公开
    INSULATED GATE BIPOLAR TRANSISTOR 审中-公开

    公开(公告)号：US20230207672A1

    公开(公告)日：2023-06-29

    申请号：US17577025

    申请日：2022-01-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Ming Hou

    IPC: H01L29/739 ,  H01L29/778 ,  H01L29/205 ,  H01L29/20

    CPC classification number: H01L29/7396 ,  H01L29/7786 ,  H01L29/205 ,  H01L29/2003

    Abstract: An insulated gate bipolar transistor includes a P-type group III-V nitride compound layer. An N-type group III-V nitride compound layer contacts a side of the P-type group III-V nitride compound layer. An HEMT is disposed on the N-type group III-V nitride compound layer. The HEMT includes a first group III-V nitride compound layer disposed on the N-type group III-V nitride compound layer. A second group III-V nitride compound layer is disposed on the first group III-V nitride compound layer. A source is embedded within the second group III-V nitride compound layer and the first group III-V nitride compound layer, wherein the source includes an N-type group III-V nitride compound body and a metal contact. A drain contacts another side of the P-type group III-V nitride compound layer. A gate is disposed on the second group III-V nitride compound layer.

    Hierarchical Wafer Lifetime Prediction Method
    5.
    发明申请
    Hierarchical Wafer Lifetime Prediction Method 有权
    分层晶圆寿命预测方法

    公开(公告)号：US20150323586A1

    公开(公告)日：2015-11-12

    申请号：US14803137

    申请日：2015-07-20

    Applicant: United Microelectronics Corp.

    Inventor： Hsin-Ming Hou ,  Ji-Fu Kung

    IPC: G01R31/26 ,  H01L21/66

    CPC classification number: G01R31/2642 ,  G06F17/50 ,  H01L22/14 ,  H01L22/20

    Abstract: For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield domain for wafer yield prediction and a lifetime domain for a wafer lifetime prediction, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised.

    Abstract translation: 为了改善晶片制造，通过确定晶片产量预测的屈服域的系数和晶片寿命预测的寿命域，整合域，电/布局域，计量/缺陷域和 机器传感器域以分层方式。 借助于层次确定的系数，可以减少预测中的噪声，从而可以提高晶片的产量或寿命的预测结果的精度。

    Hierarchical wafer lifetime prediction method
    6.
    发明授权
    Hierarchical wafer lifetime prediction method 有权

    公开(公告)号：US09958494B2

    公开(公告)日：2018-05-01

    申请号：US14803137

    申请日：2015-07-20

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Ming Hou ,  Ji-Fu Kung

    IPC: G01R31/26 ,  H01L21/66 ,  G06F17/50

    CPC classification number: G01R31/2642 ,  G06F17/50 ,  H01L22/14 ,  H01L22/20

    Abstract: For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield domain for wafer yield prediction and a lifetime domain for a wafer lifetime prediction, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised.

    COMPLEMENTARY HIGH ELECTRON MOBILITY TRANSISTOR
    7.
    发明公开
    COMPLEMENTARY HIGH ELECTRON MOBILITY TRANSISTOR 审中-公开

    公开(公告)号：US20230207679A1

    公开(公告)日：2023-06-29

    申请号：US17577042

    申请日：2022-01-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Ming Hou

    IPC: H01L29/778 ,  H01L29/20

    CPC classification number: H01L29/7787 ,  H01L29/2003

    Abstract: A complementary high electron mobility transistor includes an N-type HEMT and an P-type HEMT disposed on the substrate. The N-type HEMT includes a first undoped gallium nitride layer, a first quantum confinement channel, a first undoped group III-V nitride compound layer and an N-type group III-V nitride compound layer disposed from bottom to top. A first gate is disposed on the N-type group III-V nitride compound layer. A first source and a first drain are disposed at two sides of the first gate. The P-type HEMT includes a second undoped gallium nitride layer, a second quantum confinement channel, a second undoped group III-V nitride compound layer and a P-type group III-V nitride compound layer disposed from bottom to top. A second gate is disposed on the P-type group III-V nitride compound layer. A second source and a second drain are disposed at two sides of the second gate.

    Hierarchical Wafer Yield Prediction Method and Hierarchical Lifetime Prediction Method
    9.
    发明申请
    Hierarchical Wafer Yield Prediction Method and Hierarchical Lifetime Prediction Method 有权
    分层晶圆产量预测方法和分层寿命预测方法

    公开(公告)号：US20140089871A1

    公开(公告)日：2014-03-27

    申请号：US14099997

    申请日：2013-12-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Ming Hou ,  Ji-Fu Kung

    IPC: G06F17/50

    CPC classification number: G01R31/2642 ,  G06F17/50 ,  H01L22/14 ,  H01L22/20

    Abstract: For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield domain for wafer yield prediction and a lifetime domain for a wafer lifetime prediction, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised.

    Abstract translation: 为了改善晶片制造，通过确定晶片产量预测的屈服域的系数和晶片寿命预测的寿命域，整合域，电/布局域，计量/缺陷域和 机器传感器域以分层方式。 借助于层次确定的系数，可以减少预测中的噪声，从而可以提高晶片的产量或寿命的预测结果的精度。

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