公开(公告)号：US09564507B2

公开(公告)日：2017-02-07

申请号：US15003813

申请日：2016-01-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Lin ,  Hui-Shen Shih

IPC: H01L21/768 ,  H01L21/02 ,  H01L29/78 ,  H01L21/31 ,  H01L29/51 ,  H01L23/532 ,  H01L23/535 ,  H01L29/423

CPC classification number: H01L29/51 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76838 ,  H01L23/53295 ,  H01L23/535 ,  H01L29/42376 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first tensile dielectric layer on the substrate; a metal gate in the first tensile dielectric layer; a second tensile dielectric layer on the first tensile dielectric layer; and a contact plug in the first tensile dielectric layer and the second tensile dielectric layer. Preferably, the top surface of the contact plug is even with the top surface of the second tensile dielectric layer, and a carbon content of the second tensile dielectric layer is greater than the carbon content of the first tensile dielectric layer.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：衬底; 在所述基板上的第一拉伸介电层; 第一拉伸介电层中的金属栅极; 第一拉伸介电层上的第二拉伸电介质层; 以及第一拉伸介电层和第二拉伸介电层中的接触塞。 优选地，接触塞的顶表面与第二拉伸介电层的顶表面均匀，并且第二拉伸介电层的碳含量大于第一拉伸介电层的碳含量。

公开(公告)号：US20150228788A1

公开(公告)日：2015-08-13

申请号：US14179563

申请日：2014-02-13

Applicant: United Microelectronics Corp.

Inventor： Chun-Feng Chen ,  Wen-Yu Yang ,  Yu-Cheng Tung ,  Chun-Hsien Huang ,  Hui-Shen Shih ,  Shih-Chang Chang

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/7847 ,  H01L21/76832 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636

Abstract: A stress memorization process including the following step is provided. A gate is formed on a substrate. A low-k dielectric layer with a dielectric constant lower than 3 is formed to entirely cover the gate and the substrate. A stress layer is formed to entirely cover the low-k dielectric layer. The stress layer and the low-k dielectric layer are removed. Moreover, a semiconductor structure including a contact etch stop layer is provided. A gate is disposed on a substrate. A porous layer entirely covers the gate and the substrate. A contact etch stop layer entirely covers the porous layer, wherein the thickness of the porous layer is thinner than the thickness of the contact etch stop layer.

Abstract translation: 提供包括以下步骤的应力记忆过程。 栅极形成在基板上。 形成介电常数低于3的低k电介质层，以完全覆盖栅极和衬底。 形成应力层以完全覆盖低k电介质层。 去除应力层和低k电介质层。 此外，提供了包括接触蚀刻停止层的半导体结构。 栅极设置在基板上。 多孔层完全覆盖栅极和衬底。 接触蚀刻停止层完全覆盖多孔层，其中多孔层的厚度比接触蚀刻停止层的厚度薄。

公开(公告)号：US09281238B2

公开(公告)日：2016-03-08

申请号：US14328717

申请日：2014-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Lin ,  Hui-Shen Shih

IPC: H01L21/768 ,  H01L21/02 ,  H01L29/78 ,  H01L21/31

CPC classification number: H01L29/51 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76838 ,  H01L23/53295 ,  H01L23/535 ,  H01L29/42376 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating interlayer dielectric (ILD) layer is disclosed. The method includes the steps of first forming a first tensile dielectric layer on a substrate, and then forming a second tensile dielectric layer on the first tensile dielectric layer.

Abstract translation: 公开了一种用于制造层间电介质（ILD）层的方法。 该方法包括以下步骤：首先在衬底上形成第一拉伸电介质层，然后在第一拉伸电介质层上形成第二拉伸电介质层。

公开(公告)号：US20160013098A1

公开(公告)日：2016-01-14

申请号：US14328717

申请日：2014-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Lin ,  Hui-Shen Shih

IPC: H01L21/768

CPC classification number: H01L29/51 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76838 ,  H01L23/53295 ,  H01L23/535 ,  H01L29/42376 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating interlayer dielectric (ILD) layer is disclosed. The method includes the steps of first forming a first tensile dielectric layer on a substrate, and then forming a second tensile dielectric layer on the first tensile dielectric layer.

Abstract translation: 公开了一种用于制造层间电介质（ILD）层的方法。 该方法包括以下步骤：首先在衬底上形成第一拉伸电介质层，然后在第一拉伸电介质层上形成第二拉伸电介质层。

公开(公告)号：US20160141383A1

公开(公告)日：2016-05-19

申请号：US15003813

申请日：2016-01-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Lin ,  Hui-Shen Shih

IPC: H01L29/51 ,  H01L29/78 ,  H01L23/535 ,  H01L29/423

CPC classification number: H01L29/51 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76838 ,  H01L23/53295 ,  H01L23/535 ,  H01L29/42376 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first tensile dielectric layer on the substrate; a metal gate in the first tensile dielectric layer; a second tensile dielectric layer on the first tensile dielectric layer; and a contact plug in the first tensile dielectric layer and the second tensile dielectric layer. Preferably, the top surface of the contact plug is even with the top surface of the second tensile dielectric layer, and a carbon content of the second tensile dielectric layer is greater than the carbon content of the first tensile dielectric layer.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：衬底; 在所述基板上的第一拉伸介电层; 第一拉伸介电层中的金属栅极; 第一拉伸介电层上的第二拉伸电介质层; 以及第一拉伸介电层和第二拉伸介电层中的接触塞。 优选地，接触塞的顶表面与第二拉伸介电层的顶表面均匀，并且第二拉伸介电层的碳含量大于第一拉伸介电层的碳含量。