-
公开(公告)号：US09785046B2
公开(公告)日：2017-10-10
申请号：US14601250
申请日：2015-01-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Te-Hsien Hsieh , Ming-Jui Chen , Cheng-Te Wang , Jing-Yi Lee , Jian-Yuan Ma , Yan-Chun Chen
Abstract: The present invention provides a pattern verifying method. First, a target pattern is decomposed into a first pattern and a second pattern. A first OPC process is performed for the first pattern to form a first revised pattern, and a second OPC process is performed for the second pattern to form a second revised pattern. An inspection process is performed, wherein the inspection process comprises an after mask inspection (AMI) process, which comprises considering the target pattern, the first pattern and the second pattern.
-
公开(公告)号：US09747404B2
公开(公告)日：2017-08-29
申请号：US14807869
申请日：2015-07-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Shih-Ming Kuo , Ming-Jui Chen , Te-Hsien Hsieh , Ping-I Hsieh , Jing-Yi Lee , Yan-Chun Chen
CPC classification number: G06F17/5072 , G03F1/36 , G06F17/5081
Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.
-
公开(公告)号：US20170024506A1
公开(公告)日：2017-01-26
申请号：US14807869
申请日：2015-07-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Shih-Ming Kuo , Ming-Jui Chen , Te-Hsien Hsieh , Ping-I Hsieh , Jing-Yi Lee , Yan-Chun Chen
CPC classification number: G06F17/5072 , G03F1/36 , G06F17/5081
Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.
Abstract translation: 一种用于优化集成电路布局设计的方法包括以下步骤。 获得包括具有多个金属线的金属线特征和包括具有多个孔的孔特征的第二集成电路布局设计的第一集成电路布局设计。 通过将具有孔特征的金属线特征拼接，选择孔特征的线端孔特征。 线端孔特征通过计算机系统由相邻孔之间的间隔分为单孔特征和冗余孔特征。
-
公开(公告)号：US20160147140A1
公开(公告)日：2016-05-26
申请号：US14601250
申请日：2015-01-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Te-Hsien Hsieh , Ming-Jui Chen , Cheng-Te Wang , Jing-Yi Lee , Jian-Yuan Ma , Yan-Chun Chen
IPC: G03F1/36 , G03F1/72 , H01L21/308 , G03F1/84 , H01L21/66 , H01L21/027
Abstract: The present invention provides a pattern verifying method. First, a target pattern is decomposed into a first pattern and a second pattern. A first OPC process is performed for the first pattern to form a first revised pattern, and a second OPC process is performed for the second pattern to form a second revised pattern. An inspection process is performed, wherein the inspection process comprises an after mask inspection (AMI) process, which comprises considering the target pattern, the first pattern and the second pattern.
Abstract translation: 本发明提供一种模式验证方法。 首先，将目标图案分解为第一图案和第二图案。 对第一图案执行第一OPC处理以形成第一修订图案，并且对第二图案执行第二OPC处理以形成第二修改图案。 执行检查过程，其中检查过程包括后掩模检查（AMI）处理，其包括考虑目标图案，第一图案和第二图案。
-
-
-
Search Results
4
records
(took 0.013 seconds)
