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公开(公告)号：US09047658B2
公开(公告)日：2015-06-02
申请号：US14071667
申请日：2013-11-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Te-Hsien Hsieh , Ming-Jui Chen , Cheng-Te Wang , Ping-I Hsieh , Jing-Yi Lee
CPC classification number: G06T7/0004 , G03F1/36 , G06K9/00 , G06T7/001 , G06T2207/30148
Abstract: A calculation method of optical proximity correction includes providing at least a feature pattern to a computer system. At least a first template and a second template are defined so that portions of the feature pattern are located in the first template and the rest of the feature pattern is located in the second template. The first template and the second template have a common boundary. Afterwards, a first calculation zone is defined to overlap an entire first template and portions of the feature pattern out of the first template. Edges of the feature pattern within the first calculation zone are then fragmented from the common boundary towards two ends of the feature pattern so as to generate at least two first beginning segments respectively at two sides of the common boundary. Finally, positions of the first beginning segments are adjusted so as to generate first adjusted segments.
Abstract translation: 光学邻近校正的计算方法包括至少向计算机系统提供特征图案。 定义至少第一模板和第二模板，使得特征图案的部分位于第一模板中，并且特征图案的其余部分位于第二模板中。 第一个模板和第二个模板有一个共同的边界。 之后，定义第一计算区域以将整个第一模板和第一模板中的特征模式的部分重叠。 然后将第一计算区域内的特征图案的边缘从公共边界分割成特征图案的两端，以便分别在公共边界的两侧产生至少两个第一开始段。 最后，调整第一起始段的位置，以产生第一调整段。
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公开(公告)号：US20170024506A1
公开(公告)日：2017-01-26
申请号：US14807869
申请日：2015-07-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Shih-Ming Kuo , Ming-Jui Chen , Te-Hsien Hsieh , Ping-I Hsieh , Jing-Yi Lee , Yan-Chun Chen
CPC classification number: G06F17/5072 , G03F1/36 , G06F17/5081
Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.
Abstract translation: 一种用于优化集成电路布局设计的方法包括以下步骤。 获得包括具有多个金属线的金属线特征和包括具有多个孔的孔特征的第二集成电路布局设计的第一集成电路布局设计。 通过将具有孔特征的金属线特征拼接，选择孔特征的线端孔特征。 线端孔特征通过计算机系统由相邻孔之间的间隔分为单孔特征和冗余孔特征。
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公开(公告)号：US20160147140A1
公开(公告)日：2016-05-26
申请号：US14601250
申请日：2015-01-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Te-Hsien Hsieh , Ming-Jui Chen , Cheng-Te Wang , Jing-Yi Lee , Jian-Yuan Ma , Yan-Chun Chen
IPC: G03F1/36 , G03F1/72 , H01L21/308 , G03F1/84 , H01L21/66 , H01L21/027
Abstract: The present invention provides a pattern verifying method. First, a target pattern is decomposed into a first pattern and a second pattern. A first OPC process is performed for the first pattern to form a first revised pattern, and a second OPC process is performed for the second pattern to form a second revised pattern. An inspection process is performed, wherein the inspection process comprises an after mask inspection (AMI) process, which comprises considering the target pattern, the first pattern and the second pattern.
Abstract translation: 本发明提供一种模式验证方法。 首先，将目标图案分解为第一图案和第二图案。 对第一图案执行第一OPC处理以形成第一修订图案，并且对第二图案执行第二OPC处理以形成第二修改图案。 执行检查过程，其中检查过程包括后掩模检查（AMI）处理，其包括考虑目标图案，第一图案和第二图案。
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公开(公告)号：US09785046B2
公开(公告)日：2017-10-10
申请号：US14601250
申请日：2015-01-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Te-Hsien Hsieh , Ming-Jui Chen , Cheng-Te Wang , Jing-Yi Lee , Jian-Yuan Ma , Yan-Chun Chen
Abstract: The present invention provides a pattern verifying method. First, a target pattern is decomposed into a first pattern and a second pattern. A first OPC process is performed for the first pattern to form a first revised pattern, and a second OPC process is performed for the second pattern to form a second revised pattern. An inspection process is performed, wherein the inspection process comprises an after mask inspection (AMI) process, which comprises considering the target pattern, the first pattern and the second pattern.
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公开(公告)号：US20150036116A1
公开(公告)日：2015-02-05
申请号：US13957436
申请日：2013-08-02
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Te-Hsien Hsieh , Shih-Ming Kuo , Ming-Jui Chen , Cheng-Te Wang , Jing-Yi Lee
IPC: G03F7/20
CPC classification number: G03F7/70308 , G03F7/7025
Abstract: An aperture is configured to be disposed between an illumination source and a semiconductor substrate in a photolithography system. The aperture includes a light-transmission portion with a non-planar thickness profile to compensate the discrepancy of wave-fronts of the light beams of different orders.
Abstract translation: 孔被配置为在光刻系统中设置在照明源和半导体衬底之间。 孔径包括具有非平面厚度轮廓的光透射部分，以补偿不同阶数的光束的波前差异。
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Patent Agency Ranking
公开(公告)号：US10474026B2
公开(公告)日：2019-11-12
申请号：US15335458
申请日：2016-10-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Kuei-Hsu Chou , Cheng-Te Wang , Yung-Feng Cheng , Jing-Yi Lee
Abstract: A method of correcting a layout pattern is provided in the present invention. The method includes the following steps. A layout pattern including at least two adjacent rectangular sub patterns is provided. The layout pattern is then input into a computer system. An optical proximity correction including a bevel correction is then performed. The bevel correction includes forming a bevel at a corner of at least one of the two adjacent rectangular sub patterns, wherein the bevel is formed by chopping the corner, and moving the bevel toward an interaction of two neighboring segments of the bevel if a distance between the bevel and the other rectangular sub pattern is larger than a minimum value. The angle between a surface of the bevel and a surface of the rectangular sub pattern is not rectangular. The layout pattern is output to a mask after the optical proximity correction.
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公开(公告)号：US20180120693A1
公开(公告)日：2018-05-03
申请号：US15335458
申请日：2016-10-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Kuei-Hsu Chou , Cheng-Te Wang , Yung-Feng Cheng , Jing-Yi Lee
CPC classification number: G03F1/36 , G06F17/5081
Abstract: A method of correcting a layout pattern is provided in the present invention. The method includes the following steps. A layout pattern including at least two adjacent rectangular sub patterns is provided. The layout pattern is then input into a computer system. An optical proximity correction including a bevel correction is then performed. The bevel correction includes forming a bevel at a corner of at least one of the two adjacent rectangular sub patterns, wherein the bevel is formed by chopping the corner, and moving the bevel toward an interaction of two neighboring segments of the bevel if a distance between the bevel and the other rectangular sub pattern is larger than a minimum value. The angle between a surface of the bevel and a surface of the rectangular sub pattern is not rectangular. The layout pattern is output to a mask after the optical proximity correction.
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公开(公告)号：US09747404B2
公开(公告)日：2017-08-29
申请号：US14807869
申请日：2015-07-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Shih-Ming Kuo , Ming-Jui Chen , Te-Hsien Hsieh , Ping-I Hsieh , Jing-Yi Lee , Yan-Chun Chen
CPC classification number: G06F17/5072 , G03F1/36 , G06F17/5081
Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.
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公开(公告)号：US20150125063A1
公开(公告)日：2015-05-07
申请号：US14071667
申请日：2013-11-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Te-Hsien Hsieh , Ming-Jui Chen , Cheng-Te Wang , Ping-I Hsieh , Jing-Yi Lee
IPC: G06T7/00
CPC classification number: G06T7/0004 , G03F1/36 , G06K9/00 , G06T7/001 , G06T2207/30148
Abstract: A calculation method of optical proximity correction includes providing at least a feature pattern to a computer system. At least a first template and a second template are defined so that portions of the feature pattern are located in the first template and the rest of the feature pattern is located in the second template. The first template and the second template have a common boundary. Afterwards, a first calculation zone is defined to overlap an entire first template and portions of the feature pattern out of the first template. Edges of the feature pattern within the first calculation zone are then fragmented from the common boundary towards two ends of the feature pattern so as to generate at least two first beginning segments respectively at two sides of the common boundary. Finally, positions of the first beginning segments are adjusted so as to generate first adjusted segments.
Abstract translation: 光学邻近校正的计算方法包括至少向计算机系统提供特征图案。 定义至少第一模板和第二模板，使得特征图案的部分位于第一模板中，并且特征图案的其余部分位于第二模板中。 第一个模板和第二个模板有一个共同的边界。 之后，定义第一计算区域以将整个第一模板和第一模板中的特征模式的部分重叠。 然后将第一计算区域内的特征图案的边缘从公共边界分割成特征图案的两端，以便分别在公共边界的两侧产生至少两个第一开始段。 最后，调整第一起始段的位置，以产生第一调整段。
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公开(公告)号：US08745547B1
公开(公告)日：2014-06-03
申请号：US13940096
申请日：2013-07-11
Applicant: United Microelectronics Corp.
Inventor： Shih-Ming Kuo , Ming-Jui Chen , Te-Hsien Hsieh , Cheng-Te Wang , Jing-Yi Lee
IPC: G06F17/50
CPC classification number: G03F1/70
Abstract: A method for making a photomask layout is disclosed. A graphic data of a photomask is provided. A first correction step is performed to the graphic data. A first verification step is performed to all of the graphic data which has been subjected to the first correction step, wherein at least one failed pattern not passing the first verification step is found. A second correction step is performed to the at least one failed pattern, so as to obtain at least one modified pattern. A second verification step is performed only to at least one buffer region covering the at least one modified pattern, wherein the buffer region has an area less than a whole area of the photomask. Besides, each of the first correction step, the first verification step, the second correction step and the second verification step is executed by a computer.
Abstract translation: 公开了一种制造光掩模布局的方法。 提供光掩模的图形数据。 对图形数据执行第一校正步骤。 对已经经过第一校正步骤的所有图形数据执行第一验证步骤，其中找到不通过第一验证步骤的至少一个故障模式。 对所述至少一个故障模式执行第二校正步骤，以便获得至少一个修改的模式。 第二验证步骤仅对覆盖至少一个修改图案的至少一个缓冲区域执行，其中缓冲区域具有小于光掩模的整个区域的面积。 此外，第一校正步骤，第一校验步骤，第二校正步骤和第二校验步骤中的每一个由计算机执行。
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