公开(公告)号：US20190103405A1

公开(公告)日：2019-04-04

申请号：US15725275

申请日：2017-10-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Ting Ho ,  Sung-Bin Lin

IPC: H01L27/105 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L29/788 ,  H01L27/11517

Abstract: A manufacturing method of a semiconductor memory device includes the following steps. A gate structure is formed on a semiconductor substrate. The gate structure includes a floating gate electrode, a control gate electrode, a first oxide layer, and a second oxide layer. The control gate electrode is disposed on the floating gate electrode. The first oxide layer is disposed between the floating gate electrode and the semiconductor substrate. The second oxide layer is disposed between the floating gate electrode and the control gate electrode. An oxide spacer layer is conformally on the gate structure and the semiconductor substrate. A nitride spacer is formed on the oxide spacer layer and on a sidewall of the gate structure. An oxidation process is performed after the step of forming the nitride spacer. A thickness of an edge portion of the first oxide layer is increased by the oxidation process.

公开(公告)号：US20170317092A1

公开(公告)日：2017-11-02

申请号：US15140029

申请日：2016-04-27

Applicant: United Microelectronics Corp.

Inventor： Yen-Ting Ho ,  Sung-Bin Lin

IPC: H01L27/11521 ,  H01L29/66 ,  H01L27/11558 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/11521 ,  H01L27/11558 ,  H01L29/42328 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/7835

Abstract: A memory cell disposed on a substrate has a first gate structure and a second gate structure. The memory cell includes a first heavily doped region adjacent to an outer side of the first gate structure. Further, a first lightly doped drain (LDD) region with a first type dopant is between the first heavily doped region and the outer side of the first gate structure. A pocket doped region with a second type dopant is overlapping with the first LDD region. The second type dopant is opposite to the first type dopant in conductive type. A second heavily doped region is adjacent to an outer side of the second gate structure, opposite to the first heavily doped region. A second LDD region with the first type dopant is disposed between the first gate structure and the second gate structure.

公开(公告)号：US10510758B2

公开(公告)日：2019-12-17

申请号：US15725275

申请日：2017-10-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Ting Ho ,  Sung-Bin Lin

IPC: H01L21/30 ,  H01L27/105 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11517 ,  H01L29/51 ,  H01L29/423 ,  H01L29/788

Abstract: A manufacturing method of a semiconductor memory device includes the following steps. A gate structure is formed on a semiconductor substrate. The gate structure includes a floating gate electrode, a control gate electrode, a first oxide layer, and a second oxide layer. The control gate electrode is disposed on the floating gate electrode. The first oxide layer is disposed between the floating gate electrode and the semiconductor substrate. The second oxide layer is disposed between the floating gate electrode and the control gate electrode. An oxide spacer layer is conformally on the gate structure and the semiconductor substrate. A nitride spacer is formed on the oxide spacer layer and on a sidewall of the gate structure. An oxidation process is performed after the step of forming the nitride spacer. A thickness of an edge portion of the first oxide layer is increased by the oxidation process.

公开(公告)号：US09530511B1

公开(公告)日：2016-12-27

申请号：US14969584

申请日：2015-12-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Ting Ho ,  Sung-Bin Lin

IPC: G11C16/16 ,  G11C16/14 ,  G11C16/04 ,  H01L29/792 ,  H01L29/423 ,  G11C16/10 ,  H01L29/51

CPC classification number: G11C16/14 ,  G11C16/0466 ,  G11C16/10 ,  H01L29/4234 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/518 ,  H01L29/792

Abstract: An operating method of a memory device includes providing the memory device and performing an erase operation. The memory device includes a substrate, a gate dielectric layer formed on the substrate, a gate conductive layer formed on the gate dielectric layer, a charge trapping layer, a charge blocking layer, a source region, and a drain region. The charge trapping layer has a vertical portion formed on a sidewall of the gate conductive layer and a horizontal portion formed between the substrate and the gate conductive layer. The charge blocking layer is formed between the substrate and the charge trapping layer. The source and drain regions are formed in the substrate and located at two sides of the gate conductive layer respectively. Performing the erase operation includes applying an erase voltage to the gate conductive layer for inducing a BBHH injection and a FN hole tunneling.

Abstract translation: 存储器件的操作方法包括提供存储器件并执行擦除操作。 存储器件包括衬底，形成在衬底上的栅极电介质层，形成在栅极介电层上的栅极导电层，电荷俘获层，电荷阻挡层，源极区和漏极区。 电荷捕获层具有形成在栅极导电层的侧壁上的垂直部分和形成在基板和栅极导电层之间的水平部分。 电荷阻挡层形成在基板和电荷俘获层之间。 源极和漏极区分别形成在衬底中并分别位于栅极导电层的两侧。 执行擦除操作包括向栅极导电层施加擦除电压以引起BBHH注入和FN空穴隧穿。

公开(公告)号：US09793278B1

公开(公告)日：2017-10-17

申请号：US15140029

申请日：2016-04-27

Applicant: United Microelectronics Corp.

Inventor： Yen-Ting Ho ,  Sung-Bin Lin

IPC: H01L29/66 ,  H01L27/11 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L27/11521 ,  H01L27/11558 ,  H01L29/42328 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/7835

Abstract: A memory cell disposed on a substrate has a first gate structure and a second gate structure. The memory cell includes a first heavily doped region adjacent to an outer side of the first gate structure. Further, a first lightly doped drain (LDD) region with a first type dopant is between the first heavily doped region and the outer side of the first gate structure. A pocket doped region with a second type dopant is overlapping with the first LDD region. The second type dopant is opposite to the first type dopant in conductive type. A second heavily doped region is adjacent to an outer side of the second gate structure, opposite to the first heavily doped region. A second LDD region with the first type dopant is disposed between the first gate structure and the second gate structure.

公开(公告)号：US09136276B1

公开(公告)日：2015-09-15

申请号：US14255977

申请日：2014-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Huei Huang ,  Sung-Bin Lin ,  Wen-Chung Chang ,  Feng-Ji Tsai ,  Yen-Ting Ho ,  Chien-Hung Chen

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L21/26513 ,  H01L27/11573 ,  H01L29/42348 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: A method for forming a memory cell structure includes following steps. A substrate including at least a memory cell region defined thereon is provided, and a first gate stack is formed in the memory cell region. A first LDD implantation is performed to form a first LDD at one side of the first gate stack in the memory cell region, and the first LDD includes a first conductivity type. A second LDD implantation is performed to form a second LDD at one side of the first gate stack opposite to the first LDD in the memory cell region, and the second LDD includes the first conductivity type. The first LDD and the second LDD are different from each other.

Abstract translation: 一种用于形成存储单元结构的方法包括以下步骤。 提供至少包括限定在其上的存储单元区域的衬底，并且在存储单元区域中形成第一栅极堆叠。 执行第一LDD注入以在存储单元区域中的第一栅极堆叠的一侧形成第一LDD，并且第一LDD包括第一导电类型。 执行第二LDD注入以在存储单元区域中与第一LDD相对的第一栅极堆叠的一侧处形成第二LDD，并且第二LDD包括第一导电类型。 第一LDD和第二LDD彼此不同。