公开(公告)号：US11710661B2

公开(公告)日：2023-07-25

申请号：US17072006

申请日：2020-10-15

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Enrique Jr Sarile ,  Dzafir Bin Mohd Shariff ,  Seung Geun Park ,  Ronnie M. De Villa ,  Zhong Hai Wang

IPC: H01L21/78 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L23/3192 ,  H01L23/564

Abstract: A semiconductor package is disclosed. The semiconductor package includes a substrate with a first surface, a second surface and sidewalls. The package also includes backside metallization (BSM) over the second surface of the substrate. The semiconductor package is devoid of metal debris.

公开(公告)号：US11670549B2

公开(公告)日：2023-06-06

申请号：US17125917

申请日：2020-12-17

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Dzafir Bin Mohd Shariff ,  Enrique Jr Sarile ,  Seung Geun Park

IPC: H01L21/78 ,  H01L23/544 ,  H01L21/768

CPC classification number: H01L21/78 ,  H01L21/76838 ,  H01L23/544

Abstract: A semiconductor package which is free of metal debris from backside metallization (BSM) is disclosed. The semiconductor package is singulated by performing a saw street open process from the frontside of the wafer and then includes a singulation process using a plasma etch from the backside of the wafer with BSM. The singulation process results in metal debris free packages.

公开(公告)号：US20220336283A1

公开(公告)日：2022-10-20

申请号：US17722416

申请日：2022-04-18

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Enrique Jr Sarile ,  Chee Kay Chow ,  Dzafir Bin Mohd Shariff

IPC: H01L21/78 ,  H01L21/683 ,  H01L21/67

Abstract: A wafer adaptor ring assembly for adapting an adapted sized wafer for plasma dicing by a plasma etch chamber designed for dicing a designed sized wafer, which is larger than the adapted sized wafer is disclosed. The wafer adaptor ring assembly includes a primary wafer ring designed for plasma dicing the designed sized wafer by the plasma, an adhesive sheet attached to a bottom surface of the primary wafer ring, and an adapted sized wafer disposed on the adhesive sheet between the primary wafer ring and the adapted sized wafer. A system for assembling and disassembling the wafer adaptor ring assembly is also disclosed.

公开(公告)号：US20230154795A1

公开(公告)日：2023-05-18

申请号：US18054547

申请日：2022-11-11

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Dzafir Bin Mohd Shariff ,  IL KWON SHIM ,  Enrique Jr Sarile ,  Jackson Fernandez Rosario ,  Ronnie M. De Villa ,  Chan Loong Neo

IPC: H01L21/78 ,  H01L21/308

CPC classification number: H01L21/78 ,  H01L21/3086 ,  H01L21/3085 ,  H01L21/3081

Abstract: The present disclosure relates to plasma dicing of wafer. More specifically, the present disclosure is directed to frame masks and methods for plasma dicing wafers utilizing frame masks. The frame mask includes a mask frame, wherein the mask frame includes a top ring mask support and a side ring mask support. A plurality of mask segments suspended from the top ring mask support by segment supports, the mask segments are configured to define dicing channels on a blank wafer. The frame mask is configured to removably sit onto a frame lift assembly in a plasma chamber of a plasma dicing tool, when fitted onto the frame lift assembly, the mask segments are disposed above a wafer on a wafer ring frame for plasma dicing. The mask frame is configured to enable flow of plasma therethrough to the wafer to etch the wafer to form dicing channels defined by the mask segments.

公开(公告)号：US11177301B2

公开(公告)日：2021-11-16

申请号：US16687659

申请日：2019-11-18

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Hua Hong Tan ,  Chee Kay Chow ,  Thian Hwee Tan ,  Wedanni Linsangan Micla ,  Enrique Jr Sarile ,  Mario Arwin Fabian ,  Dennis Tresnado ,  Antonino Ii Milanes ,  Ming Koon Ang ,  Kian Soo Lim ,  Mauro Jr. Dionisio ,  Teddy Joaquin Carreon

IPC: H01L27/14 ,  H01L27/146

Abstract: A method for forming a semiconductor package is disclosed. The method includes providing a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die attach region. A die having first and second major die surfaces is attached onto the die attach region. The second major die surface is attached to the die attach region. The first major die surface includes an die active region and a cover adhesive region surrounding the die active region. The method also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the die active region. The protective cover includes a discontinuity on at least one of the side surfaces. An encapsulant is disposed on the package substrate to cover exposed portions of the package substrate, die and bond wires and side surfaces of the protective cover, while leaving the first major cover surface exposed. The discontinuity enhances adhesion of the encapsulant to the protective cover.