公开(公告)号：US10354934B2

公开(公告)日：2019-07-16

申请号：US15961839

申请日：2018-04-24

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Nathapong Suthiwongsunthorn ,  Antonio Jr. Bambalan Dimaano ,  Rui Huang ,  Hua Hong Tan ,  Kriangsak Sae Le ,  Beng Yeung Ho ,  Nelson Agbisit De Vera ,  Roel Adeva Robles ,  Wedanni Linsangan Micla

IPC: H01L23/28 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/3105 ,  H01L21/683 ,  H01L23/544 ,  H01L23/00

Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

公开(公告)号：US11177301B2

公开(公告)日：2021-11-16

申请号：US16687659

申请日：2019-11-18

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Hua Hong Tan ,  Chee Kay Chow ,  Thian Hwee Tan ,  Wedanni Linsangan Micla ,  Enrique Jr Sarile ,  Mario Arwin Fabian ,  Dennis Tresnado ,  Antonino Ii Milanes ,  Ming Koon Ang ,  Kian Soo Lim ,  Mauro Jr. Dionisio ,  Teddy Joaquin Carreon

IPC: H01L27/14 ,  H01L27/146

Abstract: A method for forming a semiconductor package is disclosed. The method includes providing a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die attach region. A die having first and second major die surfaces is attached onto the die attach region. The second major die surface is attached to the die attach region. The first major die surface includes an die active region and a cover adhesive region surrounding the die active region. The method also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the die active region. The protective cover includes a discontinuity on at least one of the side surfaces. An encapsulant is disposed on the package substrate to cover exposed portions of the package substrate, die and bond wires and side surfaces of the protective cover, while leaving the first major cover surface exposed. The discontinuity enhances adhesion of the encapsulant to the protective cover.

公开(公告)号：US09508623B2

公开(公告)日：2016-11-29

申请号：US14731484

申请日：2015-06-05

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Nathapong Suthiwongsunthorn ,  Antonio Jr. Bambalan Dimaano ,  Rui Huang ,  Hua Hong Tan ,  Kriangsak Sae Le ,  Beng Yeung Ho ,  Nelson Agbisit De Vera ,  Roel Adeva Robles ,  Wedanni Linsangan Micla

IPC: H01L21/44 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/3105 ,  H01L21/683 ,  H01L23/00 ,  H01L23/544

CPC classification number: H01L23/3135 ,  H01L21/3105 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2224/0391 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2924/1815 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

Abstract translation: 公开了用于形成半导体封装的半导体封装和方法。 该方法包括提供具有第一和第二主表面的晶片。 晶片由多个管芯和设置在晶片的第一主表面上的多个外部电触点制成。 该方法包括处理晶片。 处理晶片包括将晶片分离成多个单独的芯片。 单个管芯包括第一和第二主表面以及第一和第二侧壁，并且外部电触头形成在管芯的第一主表面上。 形成密封剂材料。 密封剂材料覆盖模具的第一和第二侧壁的至少一部分。

公开(公告)号：US12021096B2

公开(公告)日：2024-06-25

申请号：US17342546

申请日：2021-06-09

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Dennis Fernandez Tresnado ,  Mario Arwin Simon Fabian ,  Wedanni Linsangan Micla ,  Allan Pumatong Ilagan

IPC: H01L23/04 ,  H01L23/00 ,  H01L23/10 ,  H01L27/146

CPC classification number: H01L27/14618 ,  H01L23/04 ,  H01L23/10 ,  H01L23/562 ,  H01L24/32 ,  H01L27/14683 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/73265

Abstract: Semiconductor packages and methods for forming thereof are disclosed. The semiconductor package includes a package substrate having a die attach region with a die attached thereto. A protective cover is disposed over a sensor region of the die and attached to the die by a cover adhesive. The cover adhesive may serve as a standoff structure to support the protective cover. The standoff structure may be configured to form multiple cavities below the protective cover to reduce thermal stress on the protective cover. An encapsulant is disposed to cover the package substrate while leaving the top package surface exposed.

公开(公告)号：US09978658B2

公开(公告)日：2018-05-22

申请号：US15361487

申请日：2016-11-27

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Nathapong Suthiwongsunthorn ,  Antonio Jr. Bambalan Dimaano ,  Rui Huang ,  Hua Hong Tan ,  Kriangsak Sae Le ,  Beng Yeung Ho ,  Nelson Agbisit De Vera ,  Roel Adeva Robles ,  Wedanni Linsangan Micla

IPC: H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/3105 ,  H01L21/683 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L23/3135 ,  H01L21/3105 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2224/0391 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2924/1815 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.