FRAME MASK FOR SINGULATING WAFERS BY PLASMA ETCHING

    公开(公告)号:US20230154795A1

    公开(公告)日:2023-05-18

    申请号:US18054547

    申请日:2022-11-11

    CPC classification number: H01L21/78 H01L21/3086 H01L21/3085 H01L21/3081

    Abstract: The present disclosure relates to plasma dicing of wafer. More specifically, the present disclosure is directed to frame masks and methods for plasma dicing wafers utilizing frame masks. The frame mask includes a mask frame, wherein the mask frame includes a top ring mask support and a side ring mask support. A plurality of mask segments suspended from the top ring mask support by segment supports, the mask segments are configured to define dicing channels on a blank wafer. The frame mask is configured to removably sit onto a frame lift assembly in a plasma chamber of a plasma dicing tool, when fitted onto the frame lift assembly, the mask segments are disposed above a wafer on a wafer ring frame for plasma dicing. The mask frame is configured to enable flow of plasma therethrough to the wafer to etch the wafer to form dicing channels defined by the mask segments.

    PLASMA DICED WAFERS AND METHODS THEREOF
    5.
    发明公开

    公开(公告)号:US20230154796A1

    公开(公告)日:2023-05-18

    申请号:US18056726

    申请日:2022-11-18

    CPC classification number: H01L21/78 H01L23/3171

    Abstract: Reliable plasma dicing of wafers to singulate it into individual dies is disclosed. Laser processing is employed to form mask openings in a passivation stack of a processed wafer. The patterned passivation stack serves as a plasma dicing mask for plasma dicing the wafer. The sidewalls of the mask openings may be flat or vertical sidewalls. In other cases, the sidewalls of the mask openings are slanted or chamfered sidewalls. The plasma dices the wafer using first and second plasma etch steps. The first plasma etch step etches to form scalloped sidewalls on the first portion of the die and the second plasma step etches to form flat or vertical sidewalls on a second portion of the die. The second portion of the die is the lower portion of the substrate or wafer. This prevents backside notching to improve reliability.

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