公开(公告)号：US20230377896A1

公开(公告)日：2023-11-23

申请号：US18319452

申请日：2023-05-17

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Jackson Fernandez Rosario ,  Enrique E. Sarile Jr ,  Dzafir Bin Mohd Shariff ,  Ronnie M. De Villa ,  Chan Loong Neo ,  Phongsak Sawasdee

IPC: H01L21/3065 ,  H01L21/683 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L21/3065 ,  H01L21/6836 ,  H01L23/3107 ,  H01L23/4952 ,  H01L24/48 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/48247 ,  H01L2924/181

Abstract: Disclosed is a plasma diced die from the backside of the wafer using a back surface mask layer. The back surface mask layer remains on the backside of the die, serving as backside protection for the die. The plasma dicing may dice the wafer completely or partially. In the case of partial dicing, the partially diced wafer is expanded to singulate the wafer into individual dies by lateral force.

公开(公告)号：US20230154795A1

公开(公告)日：2023-05-18

申请号：US18054547

申请日：2022-11-11

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Dzafir Bin Mohd Shariff ,  IL KWON SHIM ,  Enrique Jr Sarile ,  Jackson Fernandez Rosario ,  Ronnie M. De Villa ,  Chan Loong Neo

IPC: H01L21/78 ,  H01L21/308

CPC classification number: H01L21/78 ,  H01L21/3086 ,  H01L21/3085 ,  H01L21/3081

Abstract: The present disclosure relates to plasma dicing of wafer. More specifically, the present disclosure is directed to frame masks and methods for plasma dicing wafers utilizing frame masks. The frame mask includes a mask frame, wherein the mask frame includes a top ring mask support and a side ring mask support. A plurality of mask segments suspended from the top ring mask support by segment supports, the mask segments are configured to define dicing channels on a blank wafer. The frame mask is configured to removably sit onto a frame lift assembly in a plasma chamber of a plasma dicing tool, when fitted onto the frame lift assembly, the mask segments are disposed above a wafer on a wafer ring frame for plasma dicing. The mask frame is configured to enable flow of plasma therethrough to the wafer to etch the wafer to form dicing channels defined by the mask segments.

公开(公告)号：US12165921B2

公开(公告)日：2024-12-10

申请号：US17723413

申请日：2022-04-18

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Enrique Sarile, Jr. ,  Chee Kay Chow ,  Dzafir Bin Mohd Shariff

IPC: H01L21/78 ,  B23Q1/03 ,  H01J37/32 ,  H01L21/67 ,  H01L21/683

Abstract: A wafer adaptor ring assembly for adapting an adapted sized wafer for plasma dicing by a plasma etch chamber designed for dicing a designed sized wafer, which is larger than the adapted sized wafer is disclosed. The wafer adaptor ring assembly includes a primary wafer ring designed for plasma dicing the designed sized wafer by the plasma, an adhesive sheet attached to a bottom surface of the primary wafer ring, and an adapted sized wafer disposed on the adhesive sheet between the primary wafer ring and the adapted sized wafer. A method for forming the wafer adaptor ring assembly is also disclosed.

公开(公告)号：US11710661B2

公开(公告)日：2023-07-25

申请号：US17072006

申请日：2020-10-15

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Enrique Jr Sarile ,  Dzafir Bin Mohd Shariff ,  Seung Geun Park ,  Ronnie M. De Villa ,  Zhong Hai Wang

IPC: H01L21/78 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L23/3192 ,  H01L23/564

Abstract: A semiconductor package is disclosed. The semiconductor package includes a substrate with a first surface, a second surface and sidewalls. The package also includes backside metallization (BSM) over the second surface of the substrate. The semiconductor package is devoid of metal debris.

公开(公告)号：US20220336283A1

公开(公告)日：2022-10-20

申请号：US17722416

申请日：2022-04-18

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Enrique Jr Sarile ,  Chee Kay Chow ,  Dzafir Bin Mohd Shariff

IPC: H01L21/78 ,  H01L21/683 ,  H01L21/67

Abstract: A wafer adaptor ring assembly for adapting an adapted sized wafer for plasma dicing by a plasma etch chamber designed for dicing a designed sized wafer, which is larger than the adapted sized wafer is disclosed. The wafer adaptor ring assembly includes a primary wafer ring designed for plasma dicing the designed sized wafer by the plasma, an adhesive sheet attached to a bottom surface of the primary wafer ring, and an adapted sized wafer disposed on the adhesive sheet between the primary wafer ring and the adapted sized wafer. A system for assembling and disassembling the wafer adaptor ring assembly is also disclosed.

公开(公告)号：US20220331917A1

公开(公告)日：2022-10-20

申请号：US17723413

申请日：2022-04-18

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Enrique Sarile, JR. ,  Chee Kay Chow ,  Dzafir Bin Mohd Shariff

IPC: B23Q1/03 ,  H01L21/683 ,  H01J37/32

Abstract: A wafer adaptor ring assembly for adapting an adapted sized wafer for plasma dicing by a plasma etch chamber designed for dicing a designed sized wafer, which is larger than the adapted sized wafer is disclosed. The wafer adaptor ring assembly includes a primary wafer ring designed for plasma dicing the designed sized wafer by the plasma, an adhesive sheet attached to a bottom surface of the primary wafer ring, and an adapted sized wafer disposed on the adhesive sheet between the primary wafer ring and the adapted sized wafer. A method for forming the wafer adaptor ring assembly is also disclosed.

公开(公告)号：US20250038037A1

公开(公告)日：2025-01-30

申请号：US18393621

申请日：2023-12-21

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： IL KWON SHIM ,  Dzafir Bin Mohd Shariff ,  Ronnie M. De Villa ,  Enrique E. SARILE, JR. ,  Chee Kay Chow ,  Jackson Fernandez Rosario ,  Chan Loong Neo

IPC: H01L21/683 ,  H01L21/67 ,  H01L21/687

Abstract: Lamination systems and methods of fabricating devices are disclosed. The lamination system includes multiple processing modules for delaminating a backgrinding (BG) from a surface of the wafer and laminating a dicing tape on the surface of the wafer. The system includes a wafer receiving module which is configured to hold the wafer in place with a position chuck throughout the delamination and lamination process. By using a single positioning chuck, more efficient processing is achieved. For example, there is no need to re-lign the wafer when it is moved from one chuck to another.

公开(公告)号：US20230343668A1

公开(公告)日：2023-10-26

申请号：US18302627

申请日：2023-04-18

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Il Kwon Shim ,  Ronnie M. De Villa ,  Dzafir Bin Mohd Shariff

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/3171 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/24 ,  H01L21/4846 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/20 ,  H01L24/19 ,  H01L23/3185 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2224/02381 ,  H01L2224/05083 ,  H01L2224/05111 ,  H01L2224/05008 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05569 ,  H01L2224/05647 ,  H01L2224/05611 ,  H01L2224/05655 ,  H01L2224/05644 ,  H01L2224/05639 ,  H01L2224/05571 ,  H01L2224/0401 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/245 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/24011 ,  H01L2224/05082 ,  H01L2224/05027 ,  H01L2224/05024 ,  H01L2224/05018 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2224/13124 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13116 ,  H01L2224/13113 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L23/49866 ,  H01L2224/19 ,  H01L2224/215 ,  H01L2224/2101

Abstract: A semiconductor device has a substrate and a first insulating layer formed over a first major surface of the substrate. A first redistribution layer is formed over the first insulating layer. A second insulating layer is formed over the first redistribution layer. A second redistribution layer can be formed over the second insulating layer, and a third insulating layer can be formed over the second redistribution layer. A protection layer is formed over a second major surface of the substrate for warpage control. A conductive layer is formed over the first redistribution layer, and a bump is formed over the conductive layer. An under bump metallization can be formed under the bump. The protection layer extends over a side surface of the substrate between the first major surface and second major surface. The protection layer further extends over a side surface of the first insulating layer.

公开(公告)号：US10714431B2

公开(公告)日：2020-07-14

申请号：US16057773

申请日：2018-08-07

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Antonio Bambalan Dimaano, Jr. ,  Dzafir Bin Mohd Shariff ,  Seung Guen Park ,  Roel Adeva Robles

IPC: H01L23/552 ,  H01L23/50 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: Semiconductor packages having an electromagnetic interference (EMI) shielding layer and methods for forming the same are disclosed. The method includes providing a base carrier defined with an active region and a non-active region. A fan-out redistribution structure is formed over the base carrier. A die having elongated die contacts are provided. The die contacts corresponding to conductive pillars. The die contacts are in electrical communication with the fan-out redistribution structure. An encapsulant having a first major surface and a second major surface opposite to the first major surface is formed. The encapsulant surrounds the die contacts and sidewalls of the die. An electromagnetic interference (EMI) shielding layer is formed to line the first major surface and sides of the encapsulant. An etch process is performed after forming the EMI shielding layer to completely remove the base carrier and singulate the semiconductor package.

公开(公告)号：US20230274979A1

公开(公告)日：2023-08-31

申请号：US18175124

申请日：2023-02-27

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Dzafir Bin Mohd Shariff ,  Enrique E. Sarile, JR. ,  Jackson Fernandez Rosario ,  Ronnie M. De Villa ,  Chan Loong Neo ,  Il Kwon Shim

IPC: H01L21/78 ,  H01L29/06 ,  H01L21/683

CPC classification number: H01L21/78 ,  H01L29/0657 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L21/3065

Abstract: Reliable plasma dicing of a processed wafer with a die attach film (DAF) attached to the bottom wafer surface to singulate it into individual dies is disclosed. Laser processing is employed to form mask openings in a passivation stack of a processed wafer to serve as a dicing mask. Laser processing is employed to form a modified layer with cracks on a bottom portion of the wafer. Plasma dicing partially dices the processed wafer to about the modified layer. The dicing tape is expanded laterally away from the center of the partially diced processed wafer, singulating it into individual dies. Singulation of the partially plasma diced processed wafer is facilitated by the modified layer.