公开(公告)号：US09564387B2

公开(公告)日：2017-02-07

申请号：US14794715

申请日：2015-07-08

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Saravuth Sirinorakul ,  Antonio Bambalan Dimaano, Jr. ,  Rui Huang

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/31 ,  H01L21/66 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49541 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4832 ,  H01L21/565 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48249 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/85399

Abstract: A method of and device for making a semiconductor package. The method comprises etching a first side of a metallic piece forming a leadframe with one or more wire bonding pads, applying a first protective layer on the first side, etching a second side of the metallic piece forming one or more conductive terminals, and applying a second protective layer on the second side. The semiconductor package comprises wire bonding pads in pillars structure surrounding a die attached to the leadframe. One or more terminals are on the bottom side of the semiconductor package.

Abstract translation: 一种用于制造半导体封装的方法和装置。 该方法包括使用一个或多个引线接合焊盘蚀刻形成引线框架的金属片的第一侧，在第一侧上施加第一保护层，蚀刻形成一个或多个导电端子的金属片的第二侧， 第二侧的第二保护层。 半导体封装包括围绕附接到引线框架的管芯的柱状结构的引线接合焊盘。 一个或多个端子位于半导体封装的底侧。

公开(公告)号：US09508623B2

公开(公告)日：2016-11-29

申请号：US14731484

申请日：2015-06-05

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Nathapong Suthiwongsunthorn ,  Antonio Jr. Bambalan Dimaano ,  Rui Huang ,  Hua Hong Tan ,  Kriangsak Sae Le ,  Beng Yeung Ho ,  Nelson Agbisit De Vera ,  Roel Adeva Robles ,  Wedanni Linsangan Micla

IPC: H01L21/44 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/3105 ,  H01L21/683 ,  H01L23/00 ,  H01L23/544

CPC classification number: H01L23/3135 ,  H01L21/3105 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2224/0391 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2924/1815 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

Abstract translation: 公开了用于形成半导体封装的半导体封装和方法。 该方法包括提供具有第一和第二主表面的晶片。 晶片由多个管芯和设置在晶片的第一主表面上的多个外部电触点制成。 该方法包括处理晶片。 处理晶片包括将晶片分离成多个单独的芯片。 单个管芯包括第一和第二主表面以及第一和第二侧壁，并且外部电触头形成在管芯的第一主表面上。 形成密封剂材料。 密封剂材料覆盖模具的第一和第二侧壁的至少一部分。

公开(公告)号：US09978658B2

公开(公告)日：2018-05-22

申请号：US15361487

申请日：2016-11-27

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Nathapong Suthiwongsunthorn ,  Antonio Jr. Bambalan Dimaano ,  Rui Huang ,  Hua Hong Tan ,  Kriangsak Sae Le ,  Beng Yeung Ho ,  Nelson Agbisit De Vera ,  Roel Adeva Robles ,  Wedanni Linsangan Micla

IPC: H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/3105 ,  H01L21/683 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L23/3135 ,  H01L21/3105 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2224/0391 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2924/1815 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

公开(公告)号：US20160064310A1

公开(公告)日：2016-03-03

申请号：US14794715

申请日：2015-07-08

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Saravuth Sirinorakul ,  Antonio Bambalan Dimaano, Jr. ,  Rui Huang

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/66 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49541 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4832 ,  H01L21/565 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48249 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/85399

Abstract: A method of and device for making a semiconductor package. The method comprises etching a first side of a metallic piece forming a leadframe with one or more wire bonding pads, applying a first protective layer on the first side, etching a second side of the metallic piece forming one or more conductive terminals, and applying a second protective layer on the second side. The semiconductor package comprises wire bonding pads in pillars structure surrounding a die attached to the leadframe. One or more terminals are on the bottom side of the semiconductor package.

Abstract translation: 一种用于制造半导体封装的方法和装置。 该方法包括使用一个或多个引线接合焊盘蚀刻形成引线框架的金属片的第一侧，在第一侧上施加第一保护层，蚀刻形成一个或多个导电端子的金属片的第二侧， 第二侧的第二保护层。 半导体封装包括围绕附接到引线框架的管芯的柱状结构的引线接合焊盘。 一个或多个端子位于半导体封装的底侧。

公开(公告)号：US10354934B2

公开(公告)日：2019-07-16

申请号：US15961839

申请日：2018-04-24

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Nathapong Suthiwongsunthorn ,  Antonio Jr. Bambalan Dimaano ,  Rui Huang ,  Hua Hong Tan ,  Kriangsak Sae Le ,  Beng Yeung Ho ,  Nelson Agbisit De Vera ,  Roel Adeva Robles ,  Wedanni Linsangan Micla

IPC: H01L23/28 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/3105 ,  H01L21/683 ,  H01L23/544 ,  H01L23/00

Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.